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<base href="https://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - powerpc: "Bad machine code: Using an undefined physical register""
href="https://llvm.org/bugs/show_bug.cgi?id=27943">27943</a>
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<th>Summary</th>
<td>powerpc: "Bad machine code: Using an undefined physical register"
</td>
</tr>
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<th>Product</th>
<td>new-bugs
</td>
</tr>
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<th>Version</th>
<td>3.8
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>All
</td>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>new bugs
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>vtjnash@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
</tr>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=16441" name="attach_16441" title="bugpoint-reduced powerpc64le peephole optimization bug">attachment 16441</a> <a href="attachment.cgi?id=16441&action=edit" title="bugpoint-reduced powerpc64le peephole optimization bug">[details]</a></span>
bugpoint-reduced powerpc64le peephole optimization bug
The attached code asserts when compiling with llc (no extra arguments needed),
in what appears to be a failure to update the imp-def register list during
instruction replacement by Peephole Optimizations.
The observed error message is:
```
*** Bad machine code: Using an undefined physical register ***
- function: julia_gcd_50079
- basic block: BB#4 L14 (0x7fae4202aa98)
- instruction: %vreg121<def> = COPY
- operand 1: %CR0
LLVM ERROR: Found 1 machine code errors.
```
Before peephole optimizations, the SUBFC8 is used:
```
# *** IR Dump After Machine code sinking ***:
%vreg24<def> = SUBFC8 %vreg18<kill>, %vreg12<kill>, %CARRY<imp-def>;
G8RC_and_G8RC_NOX0:%vreg24 G8RC:%vreg18,%vreg12
```
Afterwards, the `SUBFC8o` alias is used instead (this replacement is correct):
```
# *** IR Dump After Peephole Optimizations ***:
%vreg24<def> = SUBFC8o %vreg18<kill>, %vreg12<kill>, %CARRY<imp-def>;
G8RC_and_G8RC_NOX0:%vreg24 G8RC:%vreg18,%vreg12
%vreg35<def> = COPY %CR0<kill>; CRRC:%vreg35
```
However, this replacement should have added `%CR0<imp-def>`, but didn't. (the
PPCInstrInfo.td entry for `multiclass XOForm_1rc` of which this instruction is
an alias of an instance reflects this correctly.)</pre>
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