[llvm-bugs] [Bug 27931] New: PPC64 Target initDwarfEHRegSizeTable has wrong register size and there is no register 114, 115, 116

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27931

            Bug ID: 27931
           Summary: PPC64 Target initDwarfEHRegSizeTable has wrong
                    register size and there is no register 114, 115, 116
           Product: clang
           Version: trunk
          Hardware: Other
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: LLVM Codegen
          Assignee: unassignedclangbugs at nondot.org
          Reporter: bluechristlove at 163.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

In the PPC64TargetCodeGenInfo, we have one function initDwarfEHRegSizeTable to
support built in function __builtin_init_dwarf_reg_size_table. However,
according to ABI ducumentation:
http://openpowerfoundation.org/?resource_lib=power-architecture-64-bit-elf-v2-abi-specification-also-openpower-abi-for-linux-supplement
page 91 Table 2-23 and GCC supplement output (see blow example), we can find
that register 64 to register 67 width is 8 bytes, but our implementatio is 4
bytes. code is here:

  // 64-76 are various 4-byte special-purpose registers:
  // 64: mq
  // 65: lr
  // 66: ctr
  // 67: ap
  // 68-75 cr0-7
  // 76: xer
  AssignToArrayRange(Builder, Address, Four8, 64, 76);

Meanwhile, according to this table and GCC supplement output, we can find we
omit register tfhar, register tfiar, register texasr, which are numbered as
114, 115 and 116. But now, we only have 113.

  // 109: vrsave
  // 110: vscr
  // 111: spe_acc
  // 112: spefscr
  // 113: sfp
  AssignToArrayRange(Builder, Address, Four8, 109, 113);

So, we should add it.

One test code of GCC output supplement:
[code]

int arr[1024];
int main() {
  __builtin_init_dwarf_reg_size_table(arr);
  return 0;
}

[/code]

gcc t.c -S

the assembly file is:
...
.LC0:
        .quad   arr
.LC1:
        .quad   arr+1
.LC2:
        .quad   arr+2
.LC3:
        .quad   arr+3
.LC4:
        .quad   arr+4
.LC5:
        .quad   arr+5
.LC6:
        .quad   arr+6
......

addis 10,2,.LC64 at toc@ha
ld 9,.LC64 at toc@l(10)
li 10,8
stb 10,0(9)

addis 10,2,.LC65 at toc@ha
ld 9,.LC65 at toc@l(10)
li 10,8
stb 10,0(9)

addis 10,2,.LC66 at toc@ha
ld 9,.LC66 at toc@l(10)
li 10,8
stb 10,0(9)
addis 10,2,.LC67 at toc@ha
ld 9,.LC67 at toc@l(10)
li 10,8
stb 10,0(9)

addis 10,2,.LC68 at toc@ha
ld 9,.LC68 at toc@l(10)
li 10,4
stb 10,0(9)

...

addis 10,2,.LC113 at toc@ha
ld 9,.LC113 at toc@l(10)
li 10,8
stb 10,0(9)

addis 10,2,.LC114 at toc@ha
ld 9,.LC114 at toc@l(10)
li 10,8
stb 10,0(9)

addis 10,2,.LC115 at toc@ha
ld 9,.LC115 at toc@l(10)
li 10,8
stb 10,0(9)

addis 10,2,.LC116 at toc@ha
ld 9,.LC116 at toc@l(10)
li 10,8
stb 10,0(9)

....

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