[llvm-bugs] [Bug 27053] New: [AArch64] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize

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https://llvm.org/bugs/show_bug.cgi?id=27053

            Bug ID: 27053
           Summary: [AArch64] Do not lower scalar sdiv/udiv to a shifts +
                    mul sequence when optimizing for minsize
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: mcrosier at codeaurora.org
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

This was implemented for X86 in r245431 by overriding isIntDivCheap().  We
should do the same for AArch64.

>From X86ISelLowering.cpp:

bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
  // Integer division on x86 is expensive. However, when aggressively
optimizing
  // for code size, we prefer to use a div instruction, as it is usually
smaller
  // than the alternative sequence.
  // The exception to this is vector division. Since x86 doesn't have vector
  // integer division, leaving the division as-is is a loss even in terms of
  // size, because it will have to be scalarized, while the alternative code
  // sequence can be performed in vector form.
  bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
                                   Attribute::MinSize);
  return OptSize && !VT.isVector();
}

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