[llvm-bugs] [Bug 27582] New: ARM64: Backend should know about implicit masking of variable shift distances

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=27582

            Bug ID: 27582
           Summary: ARM64: Backend should know about implicit masking of
                    variable shift distances
           Product: libraries
           Version: 3.8
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: fabiang at radgametools.com
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Created attachment 16281
  --> https://llvm.org/bugs/attachment.cgi?id=16281&action=edit
Repro C file

ARM64 ASRV, LSLV, LSRV, RORV are specified in the ARMv8 ARM as interpreting the
shift distance "MOD datasize", that is, modulo 32 for 32-bit shifts and modulo
64 for 64-bit shifts.

Since C/C++ shifts larger than the register width are UB, it is desirable that
the (well-defined, portable) alternatives "x >> (y & 31)" (32-bit x) and "x >>
(y & 63)" (64-bit x) not generate an extra "and", but as of Clang-3.8 they do.

Trivial reproducer is attached: "clang -O2 -c -S -target arm64-apple-darwin
test.c".

The expected result is for f to generate "lsr w0, w0, w1; ret" and g "lsr x0,
x0, x1; ret", but with Clang-3.8 explicit ANDs are present.

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