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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - ARM64: Backend should know about implicit masking of variable shift distances"
href="https://llvm.org/bugs/show_bug.cgi?id=27582">27582</a>
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<th>Summary</th>
<td>ARM64: Backend should know about implicit masking of variable shift distances
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>3.8
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
</tr>
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<th>Status</th>
<td>NEW
</td>
</tr>
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<th>Severity</th>
<td>normal
</td>
</tr>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: AArch64
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
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<th>Reporter</th>
<td>fabiang@radgametools.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvm-bugs@lists.llvm.org
</td>
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<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=16281" name="attach_16281" title="Repro C file">attachment 16281</a> <a href="attachment.cgi?id=16281&action=edit" title="Repro C file">[details]</a></span>
Repro C file
ARM64 ASRV, LSLV, LSRV, RORV are specified in the ARMv8 ARM as interpreting the
shift distance "MOD datasize", that is, modulo 32 for 32-bit shifts and modulo
64 for 64-bit shifts.
Since C/C++ shifts larger than the register width are UB, it is desirable that
the (well-defined, portable) alternatives "x >> (y & 31)" (32-bit x) and "x >>
(y & 63)" (64-bit x) not generate an extra "and", but as of Clang-3.8 they do.
Trivial reproducer is attached: "clang -O2 -c -S -target arm64-apple-darwin
test.c".
The expected result is for f to generate "lsr w0, w0, w1; ret" and g "lsr x0,
x0, x1; ret", but with Clang-3.8 explicit ANDs are present.</pre>
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