[llvm-bugs] [Bug 25591] New: [AArch64] - i1 zextloads marked as legal; requires workaround in CodeGenPrepare::optimizeLoadExt

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https://llvm.org/bugs/show_bug.cgi?id=25591

            Bug ID: 25591
           Summary: [AArch64] - i1 zextloads marked as legal; requires
                    workaround in CodeGenPrepare::optimizeLoadExt
           Product: libraries
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: gberry at codeaurora.org
                CC: llvm-bugs at lists.llvm.org
    Classification: Unclassified

Currently the AArch64 target returns true for isLoadExtLegal(ZEXTLOAD, i64/i32,
i1).  CodeGenPrepare::optimizeLoadExt() uses isLoadExtLegal() to determine if
the pattern (and (load x) mask) will be selected as a single instruction.  (and
(load x) 1) is not selected as a single instruction for AArch64 however,
despite what isLoadExtLegal says.  There is currently a check (ActiveBits <= 1)
in optimizeLoadExt() to work around this discrepancy.  The right fix may be to
mark these i1 zextloads as Promote in the AArch64 backend.

This issue came up in the development of the following change:
http://reviews.llvm.org/D14584

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