[llvm-bugs] [Bug 25410] New: [AArch64LoadStoreOpt] Merge narrow zero stores to wider single store

[via llvm-bugs]

https://llvm.org/bugs/show_bug.cgi?id=25410

            Bug ID: 25410
           Summary: [AArch64LoadStoreOpt] Merge narrow zero stores to
                    wider single store
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: mcrosier at codeaurora.org
                CC: junbuml at codeaurora.org, llvm-bugs at lists.llvm.org
    Classification: Unclassified

In r251438 a patch for converting halfword loads into a 32-bit word load was
committed.  In a similar vein we should be able to merge adjacent zero stores
into a wider store.

E.g.,
str wzr, [x0]
str wzr, [x0, #4]

to

str xzr, [x0]

-- or --

strh wzr, [x0]
strh wzr, [x0, #2]

to

str wzr, [x0]

This optimization can be generalized, but this is the one case (I can think of)
where we don't have to shuffle bits around because we know we're writing a
zero.

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