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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - [AArch64LoadStoreOpt] Merge narrow zero stores to wider single store"
href="https://llvm.org/bugs/show_bug.cgi?id=25410">25410</a>
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<th>Summary</th>
<td>[AArch64LoadStoreOpt] Merge narrow zero stores to wider single store
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>trunk
</td>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
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<th>Component</th>
<td>Backend: AArch64
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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<th>Reporter</th>
<td>mcrosier@codeaurora.org
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</tr>
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<th>CC</th>
<td>junbuml@codeaurora.org, llvm-bugs@lists.llvm.org
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<th>Classification</th>
<td>Unclassified
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</tr></table>
<p>
<div>
<pre>In r251438 a patch for converting halfword loads into a 32-bit word load was
committed. In a similar vein we should be able to merge adjacent zero stores
into a wider store.
E.g.,
str wzr, [x0]
str wzr, [x0, #4]
to
str xzr, [x0]
-- or --
strh wzr, [x0]
strh wzr, [x0, #2]
to
str wzr, [x0]
This optimization can be generalized, but this is the one case (I can think of)
where we don't have to shuffle bits around because we know we're writing a
zero.</pre>
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