[LLVMbugs] [Bug 23925] New: InstAlias instructions are not printed if the orig instruction has duplicated operands

[bugzilla-daemon at llvm.org]

https://llvm.org/bugs/show_bug.cgi?id=23925

            Bug ID: 23925
           Summary: InstAlias instructions are not printed if the orig
                    instruction has duplicated operands
           Product: tools
           Version: trunk
          Hardware: All
                OS: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: TableGen
          Assignee: unassignedbugs at nondot.org
          Reporter: dylanmckay34 at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

In a backend I maintain, there are several instructions which take two operands
- a source1/destination register, and another source register. For example,
`MUL Rd, Rr` => `Rd = Rd * Rr`

This is implemented by have three operands in the source, but with 'let
Constraints = "$src1 = $dst".

* `tst Rd` maps to `and Rd, Rd`
* `clr Rd` maps to `eor Rd, Rd`
* `ser Rd` maps to `ldi Rd, 0xff`

The first two instructions, when printed, are not written as `tst Rd` or `clr
Rd` - they are printed as `and Rd, Rd` and `eor Rd, Rd`. The last instruction
correctly maps to `ser Rd` when printed.

It appears that instruction aliases with repeated operands in the patterns do
not work correctly with regards to the instruction printer. A brief debugging
shows that inside `printAliasInstr` in `AVRGenAsmWriter.inc` (generated by
TableGen) checks if the `MCInst` has `2` operands (presumably a brief sanity
check), before it checks whether the instruction corresponds to `tst` or `clr`
- however, the instruction always contains `3` operands - `Rd` repeated three
times, causing the conditional to never be true, and the alias to not be
printed.

In `utils/TableGen`, the `CodeGenInstAlias` class holds information about an
alias - the string pattern, the instruction that is being aliased, and the
arguments to the instruction. TableGen isn't adding duplicate operands from the
`CodeGenInstruction Result` into the `ResultOperands` field in the
`CodeGenInstAlias` if it is a duplicate.

The bug also exists on the issue tracker for AVR-LLVM here
(https://github.com/avr-llvm/llvm/issues/89). Because of this bug, we can parse
the aliases, but we must write the fully qualified, non aliases instruction in
our tests. It also makes the generated assembly a little bit less readable.

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