<html>
<head>
<base href="https://llvm.org/bugs/" />
</head>
<body><table border="1" cellspacing="0" cellpadding="8">
<tr>
<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW " title="NEW --- - InstAlias instructions are not printed if the orig instruction has duplicated operands" href="https://urldefense.proofpoint.com/v2/url?u=https-3A__llvm.org_bugs_show-5Fbug.cgi-3Fid-3D23925&d=AwMBaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=pF93YEPyB-J_PERP4DUZOJDzFVX5ZQ57vQk33wu0vio&m=MSDITCh6Ln9CgOfSgYJ8SDGGhw-kXhaCR9X7tSOEWxE&s=MRNnveYGBqBvPRU2YBSlLcYhkPUZzSQ27VRfd6Z7VPY&e=">23925</a>
</td>
</tr>
<tr>
<th>Summary</th>
<td>InstAlias instructions are not printed if the orig instruction has duplicated operands
</td>
</tr>
<tr>
<th>Product</th>
<td>tools
</td>
</tr>
<tr>
<th>Version</th>
<td>trunk
</td>
</tr>
<tr>
<th>Hardware</th>
<td>All
</td>
</tr>
<tr>
<th>OS</th>
<td>All
</td>
</tr>
<tr>
<th>Status</th>
<td>NEW
</td>
</tr>
<tr>
<th>Severity</th>
<td>normal
</td>
</tr>
<tr>
<th>Priority</th>
<td>P
</td>
</tr>
<tr>
<th>Component</th>
<td>TableGen
</td>
</tr>
<tr>
<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
</tr>
<tr>
<th>Reporter</th>
<td>dylanmckay34@gmail.com
</td>
</tr>
<tr>
<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
</td>
</tr>
<tr>
<th>Classification</th>
<td>Unclassified
</td>
</tr></table>
<p>
<div>
<pre>In a backend I maintain, there are several instructions which take two operands
- a source1/destination register, and another source register. For example,
`MUL Rd, Rr` => `Rd = Rd * Rr`
This is implemented by have three operands in the source, but with 'let
Constraints = "$src1 = $dst".
* `tst Rd` maps to `and Rd, Rd`
* `clr Rd` maps to `eor Rd, Rd`
* `ser Rd` maps to `ldi Rd, 0xff`
The first two instructions, when printed, are not written as `tst Rd` or `clr
Rd` - they are printed as `and Rd, Rd` and `eor Rd, Rd`. The last instruction
correctly maps to `ser Rd` when printed.
It appears that instruction aliases with repeated operands in the patterns do
not work correctly with regards to the instruction printer. A brief debugging
shows that inside `printAliasInstr` in `AVRGenAsmWriter.inc` (generated by
TableGen) checks if the `MCInst` has `2` operands (presumably a brief sanity
check), before it checks whether the instruction corresponds to `tst` or `clr`
- however, the instruction always contains `3` operands - `Rd` repeated three
times, causing the conditional to never be true, and the alias to not be
printed.
In `utils/TableGen`, the `CodeGenInstAlias` class holds information about an
alias - the string pattern, the instruction that is being aliased, and the
arguments to the instruction. TableGen isn't adding duplicate operands from the
`CodeGenInstruction Result` into the `ResultOperands` field in the
`CodeGenInstAlias` if it is a duplicate.
The bug also exists on the issue tracker for AVR-LLVM here
(<a href="https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_avr-2Dllvm_llvm_issues_89&d=AwMBaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=pF93YEPyB-J_PERP4DUZOJDzFVX5ZQ57vQk33wu0vio&m=MSDITCh6Ln9CgOfSgYJ8SDGGhw-kXhaCR9X7tSOEWxE&s=AODXA61bDC7nVxdGWzs882GwYXmAy48pi7eWSQmY794&e=">https://github.com/avr-llvm/llvm/issues/89</a>). Because of this bug, we can parse
the aliases, but we must write the fully qualified, non aliases instruction in
our tests. It also makes the generated assembly a little bit less readable.</pre>
</div>
</p>
<hr>
<span>You are receiving this mail because:</span>
<ul>
<li>You are on the CC list for the bug.</li>
</ul>
</body>
</html>