[llvm-bugs] [Bug 24507] New: [AArch64LoadStoreOptimizer] Pair loads of different widths; e.g., LDRW + LDRX

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https://llvm.org/bugs/show_bug.cgi?id=24507

            Bug ID: 24507
           Summary: [AArch64LoadStoreOptimizer] Pair loads of different
                    widths; e.g., LDRW + LDRX
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: AArch64
          Assignee: unassignedbugs at nondot.org
          Reporter: mcrosier at codeaurora.org
                CC: gberry at codeaurora.org, junbuml at codeaurora.org,
                    llvm-bugs at lists.llvm.org, mcrosier at codeaurora.org,
                    mssimpso at codeaurora.org
    Classification: Unclassified

>From a hot loop in 400.perlbench:

  4b345c:       b9402ff0        ldr     w16, [sp,#44]
  4b3460:       aa1703e2        mov     x2, x23
  4b3464:       f9401bfa        ldr     x26, [sp,#48]

We should be able to form a ldp from the two load instructions, despite the
fact that the two are of different sizes.  We'd need to zero out the upper bits
of x16, but I'm thinking a (ldp + and) is less expensive than (ldr + ldr).

We also need to think about more subtle things such as accessing data across
page boundaries that wouldn't have been accessed otherwise or accessing illegal
addresses (in the heap).  I believe it's safe to access anything on the stack.

This optimization is specific to loads.  We cannot easily do such an
optimization for stores.

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