[LLVMbugs] [Bug 17309] New: ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets
bugzilla-daemon at llvm.org
bugzilla-daemon at llvm.org
Fri Sep 20 14:03:15 PDT 2013
http://llvm.org/bugs/show_bug.cgi?id=17309
Bug ID: 17309
Summary: ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32
for thumb1 targets
Product: tools
Version: trunk
Hardware: PC
OS: Windows NT
Status: NEW
Severity: normal
Priority: P
Component: llc
Assignee: unassignedbugs at nondot.org
Reporter: dpeixott at codeaurora.org
CC: llvmbugs at cs.uiuc.edu
Classification: Unclassified
Created attachment 11248
--> http://llvm.org/bugs/attachment.cgi?id=11248&action=edit
thumb1-byval.ll
Summary
--------
The lowering of COPY_STRUCT_BYVAL_I32 generates the post-increment forms of
ldr/ldrh/ldrb instructions. Thumb1 does not have the post-increment form of
these instructions. If I pass the generated assembly to gcc it will complain
with an error like this:
Error: cannot honor width suffix -- `ldrb r3,[r0],#1'
The integrated assembler generates an object file with an invalid instruction
encoding.
Details
--------
The COPY_STRUCT_BYVAL_I32 instruction is used to pass structures as function
arguments by copying a structure from a source to a destination location while
respecting alignment. The instruction is a pseudo-instruction that is
implemented by custom lowering in ARMTargetLowering::EmitStructByval() at the
end of instruction selection. It looks like this function was not written to
correctly handle Thumb1 targets.
The struct is copied using LDRB_POST_IMM, LDRH_POST, and LDR_POST_IMM
instructions. These correspond to the the post-increment forms of the load
instructions. Thumb1 does not support these modes. See (for example) section
A8.8.79 of the arm manual for LDRH where only Thumb2 supports the
post-increment form (encoding T3).
I'm attaching a FileCheck-ified test case that exhibits the incorrect behavior.
To reproduce:
$ llc -mtriple thumbv5 < thumb1-byval.ll
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