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<base href="http://llvm.org/bugs/" />
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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets"
href="http://llvm.org/bugs/show_bug.cgi?id=17309">17309</a>
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<th>Summary</th>
<td>ARM backend incorrectly lowers COPY_STRUCT_BYVAL_I32 for thumb1 targets
</td>
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<th>Product</th>
<td>tools
</td>
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<th>Version</th>
<td>trunk
</td>
</tr>
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<th>Hardware</th>
<td>PC
</td>
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<th>OS</th>
<td>Windows NT
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>llc
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
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</tr>
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<th>Reporter</th>
<td>dpeixott@codeaurora.org
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</tr>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
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<th>Classification</th>
<td>Unclassified
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</tr></table>
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<div>
<pre>Created <span class=""><a href="attachment.cgi?id=11248" name="attach_11248" title="thumb1-byval.ll">attachment 11248</a> <a href="attachment.cgi?id=11248&action=edit" title="thumb1-byval.ll">[details]</a></span>
thumb1-byval.ll
Summary
--------
The lowering of COPY_STRUCT_BYVAL_I32 generates the post-increment forms of
ldr/ldrh/ldrb instructions. Thumb1 does not have the post-increment form of
these instructions. If I pass the generated assembly to gcc it will complain
with an error like this:
Error: cannot honor width suffix -- `ldrb r3,[r0],#1'
The integrated assembler generates an object file with an invalid instruction
encoding.
Details
--------
The COPY_STRUCT_BYVAL_I32 instruction is used to pass structures as function
arguments by copying a structure from a source to a destination location while
respecting alignment. The instruction is a pseudo-instruction that is
implemented by custom lowering in ARMTargetLowering::EmitStructByval() at the
end of instruction selection. It looks like this function was not written to
correctly handle Thumb1 targets.
The struct is copied using LDRB_POST_IMM, LDRH_POST, and LDR_POST_IMM
instructions. These correspond to the the post-increment forms of the load
instructions. Thumb1 does not support these modes. See (for example) section
A8.8.79 of the arm manual for LDRH where only Thumb2 supports the
post-increment form (encoding T3).
I'm attaching a FileCheck-ified test case that exhibits the incorrect behavior.
To reproduce:
$ llc -mtriple thumbv5 < thumb1-byval.ll</pre>
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