[LLVMbugs] [Bug 18103] New: Double store/load instructions don't support optional register arguments

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=18103

            Bug ID: 18103
           Summary: Double store/load instructions don't support optional
                    register arguments
           Product: libraries
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
          Assignee: unassignedbugs at nondot.org
          Reporter: joerg at NetBSD.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

For example:

strexd r4, r0, [ip]

is rejected and needs to be written as

strexd r4, r0, r1, [ip]

Official ARM documents mark the r1 register as optional. It would be nice to
support this properly.

-- 
You are receiving this mail because:
You are on the CC list for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-bugs/attachments/20131130/262d7044/attachment.html>