[LLVMbugs] [Bug 16165] New: A error on VSELECT Dagcombiner with some architecture

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=16165

            Bug ID: 16165
           Summary: A error on VSELECT Dagcombiner with some architecture
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: jaykang10 at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

I met the error while compiling the code with vector type with some
architecture. IR is as following:

define <3 x i8> @test (<3 x i8> %x) #0 {
entry:
  %cmp = icmp sgt <3 x i8> %x, zeroinitializer
  %sub = sub <3 x i8> zeroinitializer, %x
  %cond = select <3 x i1> %cmp, <3 x i8> %x, <3 x i8> %sub
  ret <3 x i8> %cond
}

I tested this IR code with llc as follows:

llc -march=arm ./test.ll -o ./test.s
llc -march=mips ./test.ll -o ./test.s

'select' IR is converted to 'vselect' dag and is combined to 'sra (X,
size(X)-1); xor (add (X, Y), Y)'. There is a problem here. If the target
support i8 type as promote integer to make size(X), size(X) has i32 type. and
then type legalize pass do widening the vector like this. 

  v4i8 = BUILD_VECTOR 0x99d90a8: i32 = Constant<7> [ID=-3], 0x99d90a8: i32 =
Constant<7> [ID=-3], 0x99d90a8: i32 = Constant<7> [ID=-3], 0x9a6c6c8: i8 =
undef

In the end, type legalizer generates a error like this "Operands must all have
the same type".

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