[LLVMbugs] [Bug 18149] New: [AArch32] VSel causes ICE from optimizeCompareInstr

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=18149

            Bug ID: 18149
           Summary: [AArch32] VSel causes ICE from optimizeCompareInstr
           Product: new-bugs
           Version: trunk
          Hardware: PC
                OS: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: weimingz at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 11673
  --> http://llvm.org/bugs/attachment.cgi?id=11673&action=edit
test case

To reproduce:
llc < test.ll

llc:
/prj/llvm-arm/home/nightly/src/community-mainline/llvm/include/llvm/CodeGen/MachineOperand.h:403:
int64_t llvm::MachineOperand::getImm() const: Assertion `isImm() && "Wrong
MachineOperand accessor"' failed.
0  llc             0x0000000000e015e2 llvm::sys::PrintStackTrace(_IO_FILE*) +
34
1  llc             0x0000000000e02aca
2  libpthread.so.0 0x00007fa18dca78f0
3  libc.so.6       0x00007fa18cb4ba75 gsignal + 53
4  libc.so.6       0x00007fa18cb4f5c0 abort + 384
5  libc.so.6       0x00007fa18cb44941 __assert_fail + 241
6  llc             0x000000000055be51
7  llc             0x0000000000562fa0
llvm::ARMBaseInstrInfo::optimizeCompareInstr(llvm::MachineInstr*, unsigned int,
unsigned int, int, int, llvm::MachineRegisterInfo const*) const + 2128
8  llc             0x00000000009e6c0e
9  llc             0x00000000009e8812
10 llc             0x0000000000d91038
llvm::FPPassManager::runOnFunction(llvm::Function&) + 568
11 llc             0x0000000000d9111b
llvm::FPPassManager::runOnModule(llvm::Module&) + 43
12 llc             0x0000000000d90b4c
llvm::legacy::PassManagerImpl::run(llvm::Module&) + 892
13 llc             0x0000000000505102
14 llc             0x0000000000505cd5 main + 261
15 libc.so.6       0x00007fa18cb36c4d __libc_start_main + 253

Reason:

The current peephole optimizing for compare inst assumes an instr that
uses CPSR has an MO for ARM Cond code.However, for VSEL instructions
(vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do
they support the modification of Cond Code. 

Patch will be sent to maillist for review

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