[LLVMbugs] [Bug 15880] New: Attempts to generate x86 rol instructions yield sub-optimal results

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=15880

            Bug ID: 15880
           Summary: Attempts to generate x86 rol instructions yield
                    sub-optimal results
           Product: libraries
           Version: 3.2
          Hardware: Macintosh
                OS: MacOS X
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: X86
          Assignee: unassignedbugs at nondot.org
          Reporter: crynoid2k7 at gmail.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified

Created attachment 10446
  --> http://llvm.org/bugs/attachment.cgi?id=10446&action=edit
tarball containing llvm and resulting x86 asm for 8,16,32, and 64 bit single
and double rotates

The x86 backend recognizes a rotate-left by N bits from an expression shifted
left by N OR'd with the same expression shifted right by the width of the
expression minus N.

It should always generate a rol instruction for 8, 16, 32, and 64 bit operands;
however, for 16 bit operands it selects a shldw instruction with the src and
dst operands equal.  While functionally correct, the opcode is suboptimal (is
there ever a scenario where shld c, X, X is preferable to rol c, X?).

Furthermore, if you perform two back-to-back rotates to an expression, the 8
and 32 bit versions use back-to-back rol instructions, the 16 bit version uses
two back-to-back shldw instructions, and the 64-bit version performs a shldq
followed by a rolq.

The same behavior manifests for right rotates.

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