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<th>Bug ID</th>
<td><a class="bz_bug_link
bz_status_NEW "
title="NEW --- - Attempts to generate x86 rol instructions yield sub-optimal results"
href="http://llvm.org/bugs/show_bug.cgi?id=15880">15880</a>
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<th>Summary</th>
<td>Attempts to generate x86 rol instructions yield sub-optimal results
</td>
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<th>Product</th>
<td>libraries
</td>
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<th>Version</th>
<td>3.2
</td>
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<th>Hardware</th>
<td>Macintosh
</td>
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<th>OS</th>
<td>MacOS X
</td>
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<th>Status</th>
<td>NEW
</td>
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<th>Severity</th>
<td>normal
</td>
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<th>Priority</th>
<td>P
</td>
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<th>Component</th>
<td>Backend: X86
</td>
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<th>Assignee</th>
<td>unassignedbugs@nondot.org
</td>
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<th>Reporter</th>
<td>crynoid2k7@gmail.com
</td>
</tr>
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<th>CC</th>
<td>llvmbugs@cs.uiuc.edu
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<th>Classification</th>
<td>Unclassified
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</tr></table>
<p>
<div>
<pre>Created <span class=""><a href="attachment.cgi?id=10446" name="attach_10446" title="tarball containing llvm and resulting x86 asm for 8,16,32, and 64 bit single and double rotates">attachment 10446</a> <a href="attachment.cgi?id=10446&action=edit" title="tarball containing llvm and resulting x86 asm for 8,16,32, and 64 bit single and double rotates">[details]</a></span>
tarball containing llvm and resulting x86 asm for 8,16,32, and 64 bit single
and double rotates
The x86 backend recognizes a rotate-left by N bits from an expression shifted
left by N OR'd with the same expression shifted right by the width of the
expression minus N.
It should always generate a rol instruction for 8, 16, 32, and 64 bit operands;
however, for 16 bit operands it selects a shldw instruction with the src and
dst operands equal. While functionally correct, the opcode is suboptimal (is
there ever a scenario where shld c, X, X is preferable to rol c, X?).
Furthermore, if you perform two back-to-back rotates to an expression, the 8
and 32 bit versions use back-to-back rol instructions, the 16 bit version uses
two back-to-back shldw instructions, and the 64-bit version performs a shldq
followed by a rolq.
The same behavior manifests for right rotates.</pre>
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