[LLVMbugs] [Bug 13241] New: ARM Assembler problem with ADR instruction

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=13241

             Bug #: 13241
           Summary: ARM Assembler problem with ADR instruction
           Product: libraries
           Version: trunk
          Platform: All
        OS/Version: All
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: richard.barton at arm.com
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


The MCInst for the ARM ADR instruction as created by the MC assembler is
re-encoded into an ADD/SUB instruction (Reproducers below)

It seems to me that there has been some re-engineering of the ADD/SUB
instructions and the ADR instruction has not been taken into account in this.

Reproduce with:

(A1 encoding)
echo 'ADR      r0,#0x40000000' | ./llvm-oss/build-none/bin/llvm-mc
-triple=armv7 -show-inst -show-encoding
        .section        __TEXT,__text,regular,pure_instructions
        adr     r0, #1073741824         @ encoding: [0x00,0x00,0x8f,0xe2]
                                        @ <MCInst #30 ADR
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Imm:1073741824>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

 echo 0x00 0x00 0x8f 0xe2 | ./llvm-oss/build-none/bin/llvm-mc -triple=armv7
-show-inst -show-encoding -disassemble 
        .section        __TEXT,__text,regular,pure_instructions
        add     r0, pc, #0              @ encoding: [0x00,0x00,0x8f,0xe2]
                                        @ <MCInst #24 ADDri
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Reg:43>
                                        @  <MCOperand Imm:0>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>
                                        @  <MCOperand Reg:0>>

(A2 encoding)
echo 'ADR      r0,#-0x0' | ./llvm-oss/build-none/bin/llvm-mc -triple=armv7
-show-inst -show-encoding
        .section        __TEXT,__text,regular,pure_instructions
        adr     r0, #-2147483648        @ encoding: [0x00,0x00,0x4f,0xe2]
                                        @ <MCInst #30 ADR
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Imm:-2147483648>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

echo 0x00 0x00 0x4f 0xe2 | ./llvm-oss/build-none/bin/llvm-mc -triple=armv7
-show-inst -show-encoding -disassemble
        .section        __TEXT,__text,regular,pure_instructions
        sub     r0, pc, #0              @ encoding: [0x00,0x00,0x4f,0xe2]
                                        @ <MCInst #456 SUBri
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Reg:43>
                                        @  <MCOperand Imm:0>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>
                                        @  <MCOperand Reg:0>>

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