[LLVMbugs] [Bug 13240] New: ARM PLD/PLDW (register) with -ve Rm and a right-shift by #32 reencodes as +ve Rm

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=13240

             Bug #: 13240
           Summary: ARM PLD/PLDW (register) with -ve Rm and a right-shift
                    by #32 reencodes as +ve Rm
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: Windows NT
            Status: NEW
          Severity: normal
          Priority: P
         Component: Backend: ARM
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: apazos at codeaurora.org
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


Created attachment 8794
  --> http://llvm.org/bugs/attachment.cgi?id=8794
Correct handling imm5 value in getLdStSORegOpValue

In ARM mode PLD/PLDW (register) with -ve Rm and a right-shift by #32 is
re-encoded with Rm +ve.

Reproduce with:

echo 'PLD [r0,-r0,LSR #32]' | .../llvm-mc -triple armv7 -show-encoding
-show-inst
        .section        __TEXT,__text,regular,pure_instructions
        pld     [r0, -r0, lsr #32]      @ encoding: [0x20,0xf0,0xd0,0xf7]
                                        @ <MCInst #287 PLDrs
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Imm:28704>>

Note the same error happens with memory instructions like LDR.

This happens because getLdStSORegOpValue function is not enforcing imm5
(function defined in lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp). The
correct code should be:

-  Binary |= ShImm << 7;
+  Binary |= (ShImm&0x1f) << 7;


Fixed the function and this is the new MC output:

echo pld [r0, -r0, lsr #32] | llvm-mc -show-inst -show-encoding
        .section        __TEXT,__text,regular,pure_instructions
        pld     [r0, -r0, lsr #32]      @ encoding: [0x20,0xf0,0x50,0xf7]
                                        @ <MCInst #287 PLDrs
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Imm:28704>>

echo 0x20 0xf0 0x50 0xf7 |llvm-mc -show-inst -show-encoding -disassemble
        .section        __TEXT,__text,regular,pure_instructions
        pld     [r0, -r0]               @ encoding: [0x20,0xf0,0x50,0xf7]
                                        @ <MCInst #287 PLDrs
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Reg:60>
                                        @  <MCOperand Imm:28672>>

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