[LLVMbugs] [Bug 11902] New: Scheduler produces bogus machine code

[bugzilla-daemon at llvm.org]

http://llvm.org/bugs/show_bug.cgi?id=11902

             Bug #: 11902
           Summary: Scheduler produces bogus machine code
           Product: libraries
           Version: trunk
          Platform: PC
        OS/Version: All
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: Common Code Generator Code
        AssignedTo: unassignedbugs at nondot.org
        ReportedBy: asl at math.spbu.ru
                CC: llvmbugs at cs.uiuc.edu
    Classification: Unclassified


Created attachment 7980
  --> http://llvm.org/bugs/attachment.cgi?id=7980
Testcase

Consider the attached .ll file.

If one will feed it to llc -arm-enable-ehabi then one will see that the .vsave
entry contains spurious s18 register added to the register list. This is
because post-ra scheduler adds bogus s18 impdef operand to VSTMDDB_UPD. Adding
-disable-post-ra fixes this problem.

I can surely ignore imp-def operands in the ARM unwinding stuff emitter. But I
think this is a symptom of some bug inside the scheduler or some passes around
(I must admit, I have another testcase which is fails w/o -disable-post-ra and
passes otherwise, but I failed to reduce it yet since it's several KLOCs of
heavy vector NEON code).

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