[llvm-branch-commits] [llvm] [CodeGen][AMDGPU] Add opt-in partial SGPR spills (PR #225220)

[Christudasan Devadasan via llvm-branch-commits]

cdevadas wrote:

At first glance, the problem seems generic and should be fixed in the generic RA framework during spilling. The issue is that two tuples share the same stack slot but intend to spill only distinct subreg components (no overlap in their subregIds) based on their live components, and later, when we reload, the respective indices should be correctly restored. The actual problem described by @yxsamliu indicates a potential implementation bug in the lane-shared spilling. 
I'm going to spend some time to understand the existing mechanism and why it spills the entire register tuple even if the tuple is partially live. I suspect an incorrect liveness info leading to this incorrect spill choice.


https://github.com/llvm/llvm-project/pull/225220