[llvm-branch-commits] [clang] [CIR][CodeGen][NFC] Share requiresAMDGPUProtectedVisibility (PR #227261)
Henrich Lauko via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 29 03:26:34 PDT 2026
https://github.com/xlauko created https://github.com/llvm/llvm-project/pull/227261
Both CodeGens carry the same attribute check deciding whether an AMDGPU
kernel or device variable with hidden visibility must be promoted to
protected. The shared version takes a bool saying whether the global
currently has hidden visibility. Classic passed an llvm::GlobalValue and
CIR a cir::VisibilityKind, and both only compared it against hidden.
No functional change.
>From 75cd33345958c923ec561ae9c6a7688b92db671e Mon Sep 17 00:00:00 2001
From: Henrich Lauko <hlauko at nvidia.com>
Date: Tue, 29 Sep 2026 09:56:39 +0000
Subject: [PATCH] [CIR][CodeGen][NFC] Share requiresAMDGPUProtectedVisibility
Both CodeGens carry the same attribute check deciding whether an AMDGPU
kernel or device variable with hidden visibility must be promoted to
protected. The shared version takes a bool saying whether the global
currently has hidden visibility. Classic passed an llvm::GlobalValue and
CIR a cir::VisibilityKind, and both only compared it against hidden.
No functional change.
---
clang/include/clang/CodeGenUtils/TargetUtils.h | 6 ++++++
clang/lib/CIR/CodeGen/TargetInfo.cpp | 8 ++++++--
clang/lib/CIR/CodeGen/TargetInfo.h | 4 ----
clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp | 14 --------------
clang/lib/CodeGen/Targets/AMDGPU.cpp | 18 +++---------------
clang/lib/CodeGenUtils/TargetUtils.cpp | 14 ++++++++++++++
6 files changed, 29 insertions(+), 35 deletions(-)
diff --git a/clang/include/clang/CodeGenUtils/TargetUtils.h b/clang/include/clang/CodeGenUtils/TargetUtils.h
index 2216484dbea36..a44541c572590 100644
--- a/clang/include/clang/CodeGenUtils/TargetUtils.h
+++ b/clang/include/clang/CodeGenUtils/TargetUtils.h
@@ -19,6 +19,7 @@
#include <cstdint>
namespace clang {
+class Decl;
class FunctionDecl;
} // namespace clang
@@ -52,6 +53,11 @@ ArmSMEInlinability getArmSMEInlinability(const FunctionDecl *Caller,
/// TODO: Make this return false for SISD builtins.
bool hasExtraNeonArgument(unsigned BuiltinID);
+/// Returns whether \p D must be given protected visibility on AMDGPU.
+/// \p HasHiddenVisibility is whether the emitted global currently has hidden
+/// visibility.
+bool requiresAMDGPUProtectedVisibility(const Decl *D, bool HasHiddenVisibility);
+
} // namespace clang::CodeGenUtils
#endif // LLVM_CLANG_CODEGENUTILS_TARGETUTILS_H
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp b/clang/lib/CIR/CodeGen/TargetInfo.cpp
index 57bc5f167e460..b648ca1f2cd74 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp
@@ -7,6 +7,7 @@
#include "clang/CIR/Dialect/IR/CIRAttrs.h"
#include "clang/CIR/Dialect/IR/CIRDialect.h"
#include "clang/CIR/MissingFeatures.h"
+#include "clang/CodeGenUtils/TargetUtils.h"
using namespace clang;
using namespace clang::CIRGen;
@@ -91,13 +92,16 @@ class AMDGPUTargetCIRGenInfo : public TargetCIRGenInfo {
void setTargetAttributes(const clang::Decl *decl, mlir::Operation *global,
CIRGenModule &cgm) const override {
if (auto func = mlir::dyn_cast<cir::FuncOp>(global)) {
- if (requiresAMDGPUProtectedVisibility(decl, func.getGlobalVisibility())) {
+ if (CodeGenUtils::requiresAMDGPUProtectedVisibility(
+ decl,
+ func.getGlobalVisibility() == cir::VisibilityKind::Hidden)) {
func.setGlobalVisibility(cir::VisibilityKind::Protected);
func.setDSOLocal(true);
}
setAMDGPUTargetFunctionAttributes(decl, func, cgm);
} else if (auto gv = mlir::dyn_cast<cir::GlobalOp>(global)) {
- if (requiresAMDGPUProtectedVisibility(decl, gv.getGlobalVisibility())) {
+ if (CodeGenUtils::requiresAMDGPUProtectedVisibility(
+ decl, gv.getGlobalVisibility() == cir::VisibilityKind::Hidden)) {
gv.setGlobalVisibility(cir::VisibilityKind::Protected);
gv.setDSOLocal(true);
}
diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h b/clang/lib/CIR/CodeGen/TargetInfo.h
index e094fa53561f5..affb09f3c85d3 100644
--- a/clang/lib/CIR/CodeGen/TargetInfo.h
+++ b/clang/lib/CIR/CodeGen/TargetInfo.h
@@ -179,10 +179,6 @@ class TargetCIRGenInfo {
std::unique_ptr<TargetCIRGenInfo>
createAMDGPUTargetCIRGenInfo(CIRGenTypes &cgt);
-/// Check if AMDGPU protected visibility is required.
-bool requiresAMDGPUProtectedVisibility(const clang::Decl *d,
- cir::VisibilityKind visibility);
-
/// Set AMDGPU-specific function attributes for HIP kernels.
void setAMDGPUTargetFunctionAttributes(const clang::Decl *decl,
cir::FuncOp func, CIRGenModule &cgm);
diff --git a/clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp b/clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
index 7f1d903853660..5f3b848ed9cb6 100644
--- a/clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
+++ b/clang/lib/CIR/CodeGen/Targets/AMDGPU.cpp
@@ -23,20 +23,6 @@
using namespace clang;
using namespace clang::CIRGen;
-bool clang::CIRGen::requiresAMDGPUProtectedVisibility(
- const Decl *d, cir::VisibilityKind visibility) {
- if (visibility != cir::VisibilityKind::Hidden)
- return false;
-
- return !d->hasAttr<OMPDeclareTargetDeclAttr>() &&
- (d->hasAttr<DeviceKernelAttr>() ||
- (isa<FunctionDecl>(d) && d->hasAttr<CUDAGlobalAttr>()) ||
- (isa<VarDecl>(d) &&
- (d->hasAttr<CUDADeviceAttr>() || d->hasAttr<CUDAConstantAttr>() ||
- cast<VarDecl>(d)->getType()->isCUDADeviceBuiltinSurfaceType() ||
- cast<VarDecl>(d)->getType()->isCUDADeviceBuiltinTextureType())));
-}
-
namespace {
/// Handle amdgpu-flat-work-group-size attribute.
diff --git a/clang/lib/CodeGen/Targets/AMDGPU.cpp b/clang/lib/CodeGen/Targets/AMDGPU.cpp
index 0b5ed1898f138..607442c899f87 100644
--- a/clang/lib/CodeGen/Targets/AMDGPU.cpp
+++ b/clang/lib/CodeGen/Targets/AMDGPU.cpp
@@ -9,6 +9,7 @@
#include "ABIInfoImpl.h"
#include "TargetInfo.h"
#include "clang/AST/DeclCXX.h"
+#include "clang/CodeGenUtils/TargetUtils.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/IR/MemoryModelRelaxationAnnotations.h"
@@ -325,20 +326,6 @@ class AMDGPUTargetCodeGenInfo : public TargetCodeGenInfo {
};
}
-static bool requiresAMDGPUProtectedVisibility(const Decl *D,
- llvm::GlobalValue *GV) {
- if (GV->getVisibility() != llvm::GlobalValue::HiddenVisibility)
- return false;
-
- return !D->hasAttr<OMPDeclareTargetDeclAttr>() &&
- (D->hasAttr<DeviceKernelAttr>() ||
- (isa<FunctionDecl>(D) && D->hasAttr<CUDAGlobalAttr>()) ||
- (isa<VarDecl>(D) &&
- (D->hasAttr<CUDADeviceAttr>() || D->hasAttr<CUDAConstantAttr>() ||
- cast<VarDecl>(D)->getType()->isCUDADeviceBuiltinSurfaceType() ||
- cast<VarDecl>(D)->getType()->isCUDADeviceBuiltinTextureType())));
-}
-
void AMDGPUTargetCodeGenInfo::setFunctionDeclAttributes(
const FunctionDecl *FD, llvm::Function *F, CodeGenModule &M) const {
const auto *ReqdWGS =
@@ -454,7 +441,8 @@ void AMDGPUTargetCodeGenInfo::setFunctionDeclAttributes(
void AMDGPUTargetCodeGenInfo::setTargetAttributes(
const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
- if (requiresAMDGPUProtectedVisibility(D, GV)) {
+ if (CodeGenUtils::requiresAMDGPUProtectedVisibility(
+ D, GV->getVisibility() == llvm::GlobalValue::HiddenVisibility)) {
GV->setVisibility(llvm::GlobalValue::ProtectedVisibility);
GV->setDSOLocal(true);
}
diff --git a/clang/lib/CodeGenUtils/TargetUtils.cpp b/clang/lib/CodeGenUtils/TargetUtils.cpp
index 401e361e8743d..f72218f4dda2d 100644
--- a/clang/lib/CodeGenUtils/TargetUtils.cpp
+++ b/clang/lib/CodeGenUtils/TargetUtils.cpp
@@ -72,4 +72,18 @@ bool hasExtraNeonArgument(unsigned BuiltinID) {
return mask != 0;
}
+bool requiresAMDGPUProtectedVisibility(const Decl *D,
+ bool HasHiddenVisibility) {
+ if (!HasHiddenVisibility)
+ return false;
+
+ return !D->hasAttr<OMPDeclareTargetDeclAttr>() &&
+ (D->hasAttr<DeviceKernelAttr>() ||
+ (isa<FunctionDecl>(D) && D->hasAttr<CUDAGlobalAttr>()) ||
+ (isa<VarDecl>(D) &&
+ (D->hasAttr<CUDADeviceAttr>() || D->hasAttr<CUDAConstantAttr>() ||
+ cast<VarDecl>(D)->getType()->isCUDADeviceBuiltinSurfaceType() ||
+ cast<VarDecl>(D)->getType()->isCUDADeviceBuiltinTextureType())));
+}
+
} // namespace clang::CodeGenUtils
More information about the llvm-branch-commits
mailing list