[llvm-branch-commits] [llvm] [AMDGPU] Use a disjoint scope domain for noalias kernel arguments (PR #218770)
Krzysztof Drewniak via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Sep 28 21:57:15 PDT 2026
https://github.com/krzysz00 updated https://github.com/llvm/llvm-project/pull/218770
>From 8a905266c3111bee82ebc67be6ef5b02a525750d Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Thu, 20 Aug 2026 21:57:05 +0000
Subject: [PATCH] [AMDGPU] Use a disjoint scope domain for noalias kernel
arguments
All noalias arguments of a kernel are disjoint with each other, so we
can use a disjoint scope to save on metadata construction.
AI disclosure: Claude wrote this, I looked at it and wrote this
message.
---
.../AMDGPU/AMDGPULowerKernelArguments.cpp | 32 +--
llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 8 +-
...rnel-arguments-noalias-call-no-ptr-args.ll | 22 +-
.../CodeGen/AMDGPU/lower-noalias-kernargs.ll | 195 ++++++++----------
.../AMDGPU/si-split-load-store-alias-info.ll | 16 +-
5 files changed, 132 insertions(+), 141 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
index f0d1f90ca5c2c..87436f4915c74 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
@@ -81,10 +81,13 @@ static void addAliasScopeMetadata(Function &F, const DataLayout &DL,
if (NoAliasArgs.empty())
return;
- // Add alias scopes for each noalias argument.
+ // Add alias scopes for each noalias argument. The scopes are disjoint, since
+ // an access based on one noalias argument can't reach memory an access based
+ // on another one reaches.
MDBuilder MDB(F.getContext());
DenseMap<const Argument *, MDNode *> NewScopes;
- MDNode *NewDomain = MDB.createAnonymousAliasScopeDomain(F.getName());
+ MDNode *NewDomain =
+ MDB.createAnonymousAliasScopeDomain(F.getName(), /*DisjointScopes=*/true);
for (unsigned I = 0u; I < NoAliasArgs.size(); ++I) {
const Argument *Arg = NoAliasArgs[I];
@@ -164,17 +167,6 @@ static void addAliasScopeMetadata(Function &F, const DataLayout &DL,
if (IsUnrestrictedCall)
RequiresNoCaptureBefore = true;
- // Collect noalias scopes for instruction.
- for (const Argument *Arg : NoAliasArgs) {
- if (ObjSet.contains(Arg))
- continue;
-
- if (!RequiresNoCaptureBefore ||
- !capturesAnything(PointerMayBeCapturedBefore(
- Arg, false, I, &DT, false, CaptureComponents::Provenance)))
- NoAliases.push_back(NewScopes[Arg]);
- }
-
// Collect scopes for alias.scope metadata. Skip unrestricted calls: they
// may touch memory beyond their pointer arguments' pointees.
if (!UsesAliasingPtr && !IsUnrestrictedCall)
@@ -183,6 +175,20 @@ static void addAliasScopeMetadata(Function &F, const DataLayout &DL,
Scopes.push_back(NewScopes[Arg]);
}
+ // Collect noalias scopes for the instruction not implied by its scopes.
+ // Scopes is only non-empty when no underlying object is an escape source
+ // and the instruction isn't an unrestricted call.
+ if (Scopes.empty())
+ for (const Argument *Arg : NoAliasArgs) {
+ if (ObjSet.contains(Arg))
+ continue;
+
+ if (!RequiresNoCaptureBefore ||
+ !capturesAnything(PointerMayBeCapturedBefore(
+ Arg, false, I, &DT, false, CaptureComponents::Provenance)))
+ NoAliases.push_back(NewScopes[Arg]);
+ }
+
// Add noalias metadata to instruction.
if (!NoAliases.empty()) {
MDNode *NewMD =
diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll b/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
index b166549089f34..cd135fe68c5a2 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-kernargs.ll
@@ -1928,10 +1928,10 @@ attributes #1 = { nounwind "amdgpu-implicitarg-num-bytes"="40" }
; HSA: [[META5]] = !{i64 1024}
; HSA: [[META6]] = !{[[META7:![0-9]+]]}
; HSA: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]], !"ptr"}
-; HSA: [[META8]] = distinct !{[[META8]], i1 false, !"kern_noalias_global_ptr"}
+; HSA: [[META8]] = distinct !{[[META8]], i1 true, !"kern_noalias_global_ptr"}
; HSA: [[META9]] = !{[[META10:![0-9]+]], [[META12:![0-9]+]]}
; HSA: [[META10]] = distinct !{[[META10]], [[META11:![0-9]+]], !"ptr0"}
-; HSA: [[META11]] = distinct !{[[META11]], i1 false, !"kern_noalias_global_ptr_x2"}
+; HSA: [[META11]] = distinct !{[[META11]], i1 true, !"kern_noalias_global_ptr_x2"}
; HSA: [[META12]] = distinct !{[[META12]], [[META11]], !"ptr1"}
;.
; MESA: [[META0]] = !{}
@@ -1942,9 +1942,9 @@ attributes #1 = { nounwind "amdgpu-implicitarg-num-bytes"="40" }
; MESA: [[META5]] = !{i64 1024}
; MESA: [[META6]] = !{[[META7:![0-9]+]]}
; MESA: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]], !"ptr"}
-; MESA: [[META8]] = distinct !{[[META8]], i1 false, !"kern_noalias_global_ptr"}
+; MESA: [[META8]] = distinct !{[[META8]], i1 true, !"kern_noalias_global_ptr"}
; MESA: [[META9]] = !{[[META10:![0-9]+]], [[META12:![0-9]+]]}
; MESA: [[META10]] = distinct !{[[META10]], [[META11:![0-9]+]], !"ptr0"}
-; MESA: [[META11]] = distinct !{[[META11]], i1 false, !"kern_noalias_global_ptr_x2"}
+; MESA: [[META11]] = distinct !{[[META11]], i1 true, !"kern_noalias_global_ptr_x2"}
; MESA: [[META12]] = distinct !{[[META12]], [[META11]], !"ptr1"}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll b/llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
index 63e664bbab67a..55f1b3872bcc0 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-kernel-arguments-noalias-call-no-ptr-args.ll
@@ -22,8 +22,8 @@ define amdgpu_kernel void @call_without_ptr_args(ptr addrspace(1) noalias %out,
; CHECK-NEXT: [[IN_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 8, !invariant.load [[META0]]
; CHECK-NEXT: [[VAL:%.*]] = call i32 @memory_read_no_ptr_args(), !noalias [[META1:![0-9]+]]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[IN_LOAD]], i32 [[VAL]]
-; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META5:![0-9]+]], !noalias [[META6:![0-9]+]]
-; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META6]], !noalias [[META5]]
+; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META5:![0-9]+]]
+; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META6:![0-9]+]]
; CHECK-NEXT: ret void
;
%val = call i32 @memory_read_no_ptr_args()
@@ -68,8 +68,8 @@ define amdgpu_kernel void @argmemonly_call_without_ptr_args(ptr addrspace(1) noa
; CHECK-NEXT: [[IN_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 8, !invariant.load [[META0]]
; CHECK-NEXT: [[VAL:%.*]] = call i32 @argmemonly_read_no_ptr_args(), !noalias [[META10:![0-9]+]]
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[IN_LOAD]], i32 [[VAL]]
-; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META14:![0-9]+]], !noalias [[META15:![0-9]+]]
-; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META15]], !noalias [[META14]]
+; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !alias.scope [[META14:![0-9]+]]
+; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META15:![0-9]+]]
; CHECK-NEXT: ret void
;
%val = call i32 @argmemonly_read_no_ptr_args()
@@ -92,9 +92,9 @@ define amdgpu_kernel void @argmemonly_call_with_ptr_arg(ptr addrspace(1) noalias
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 16, !invariant.load [[META0]]
; CHECK-NEXT: [[IN_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ARGMEMONLY_CALL_WITH_PTR_ARG_KERNARG_SEGMENT]], i64 8
; CHECK-NEXT: [[IN_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 8, !invariant.load [[META0]]
-; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) [[IN_LOAD]], align 4, !alias.scope [[META16:![0-9]+]], !noalias [[META19:![0-9]+]]
-; CHECK-NEXT: call void @argmemonly_with_ptr_arg(ptr addrspace(1) [[OUT_LOAD]]), !alias.scope [[META19]], !noalias [[META16]]
-; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META19]], !noalias [[META16]]
+; CHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(1) [[IN_LOAD]], align 4, !alias.scope [[META16:![0-9]+]]
+; CHECK-NEXT: call void @argmemonly_with_ptr_arg(ptr addrspace(1) [[OUT_LOAD]]), !alias.scope [[META19:![0-9]+]]
+; CHECK-NEXT: store i32 [[LOAD]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META19]]
; CHECK-NEXT: ret void
;
%load = load i32, ptr addrspace(1) %in, align 4
@@ -112,22 +112,22 @@ attributes #4 = { nounwind memory(argmem: readwrite) }
; CHECK: [[META0]] = !{}
; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META4:![0-9]+]]}
; CHECK: [[META2]] = distinct !{[[META2]], [[META3:![0-9]+]], !"out"}
-; CHECK: [[META3]] = distinct !{[[META3]], i1 false, !"call_without_ptr_args"}
+; CHECK: [[META3]] = distinct !{[[META3]], i1 true, !"call_without_ptr_args"}
; CHECK: [[META4]] = distinct !{[[META4]], [[META3]], !"in"}
; CHECK: [[META5]] = !{[[META4]]}
; CHECK: [[META6]] = !{[[META2]]}
; CHECK: [[META7]] = !{[[META8:![0-9]+]]}
; CHECK: [[META8]] = distinct !{[[META8]], [[META9:![0-9]+]], !"out"}
-; CHECK: [[META9]] = distinct !{[[META9]], i1 false, !"readnone_call_without_ptr_args"}
+; CHECK: [[META9]] = distinct !{[[META9]], i1 true, !"readnone_call_without_ptr_args"}
; CHECK: [[META10]] = !{[[META11:![0-9]+]], [[META13:![0-9]+]]}
; CHECK: [[META11]] = distinct !{[[META11]], [[META12:![0-9]+]], !"out"}
-; CHECK: [[META12]] = distinct !{[[META12]], i1 false, !"argmemonly_call_without_ptr_args"}
+; CHECK: [[META12]] = distinct !{[[META12]], i1 true, !"argmemonly_call_without_ptr_args"}
; CHECK: [[META13]] = distinct !{[[META13]], [[META12]], !"in"}
; CHECK: [[META14]] = !{[[META13]]}
; CHECK: [[META15]] = !{[[META11]]}
; CHECK: [[META16]] = !{[[META17:![0-9]+]]}
; CHECK: [[META17]] = distinct !{[[META17]], [[META18:![0-9]+]], !"in"}
-; CHECK: [[META18]] = distinct !{[[META18]], i1 false, !"argmemonly_call_with_ptr_arg"}
+; CHECK: [[META18]] = distinct !{[[META18]], i1 true, !"argmemonly_call_with_ptr_arg"}
; CHECK: [[META19]] = !{[[META20:![0-9]+]]}
; CHECK: [[META20]] = distinct !{[[META20]], [[META18]], !"out"}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll b/llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
index 4411c0021ba80..7ab06737ded0a 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-noalias-kernargs.ll
@@ -37,9 +37,9 @@ define amdgpu_kernel void @aliasinfo_2i32_NA(ptr addrspace(1) noalias %out, ptr
; CHECK-NEXT: [[IN_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[IN_GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[IN_LOAD]], i32 [[TID]]
-; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[IN_GEP]], align 4, !alias.scope [[META1:![0-9]+]], !noalias [[META4:![0-9]+]]
+; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[IN_GEP]], align 4, !alias.scope [[META1:![0-9]+]]
; CHECK-NEXT: [[CTLZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[VAL]], i1 false) #[[ATTR5]]
-; CHECK-NEXT: store i32 [[CTLZ]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META4]], !noalias [[META1]]
+; CHECK-NEXT: store i32 [[CTLZ]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META4:![0-9]+]]
; CHECK-NEXT: ret void
;
entry:
@@ -87,9 +87,9 @@ define amdgpu_kernel void @aliasinfo_2i32_NA_AS(ptr addrspace(1) noalias %out, p
; CHECK-NEXT: [[IN_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[IN_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[IN_GEP:%.*]] = getelementptr i32, ptr addrspace(1) [[IN_LOAD]], i32 [[TID]]
-; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[IN_GEP]], align 4, !alias.scope [[META11:![0-9]+]], !noalias [[META14:![0-9]+]]
+; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr addrspace(1) [[IN_GEP]], align 4, !alias.scope [[META11:![0-9]+]], !noalias [[META9]]
; CHECK-NEXT: [[CTLZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[VAL]], i1 false) #[[ATTR5]]
-; CHECK-NEXT: store i32 [[CTLZ]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META14]], !noalias [[META11]]
+; CHECK-NEXT: store i32 [[CTLZ]], ptr addrspace(1) [[OUT_LOAD]], align 4, !alias.scope [[META14:![0-9]+]], !noalias [[META6]]
; CHECK-NEXT: ret void
;
entry:
@@ -154,12 +154,12 @@ define amdgpu_kernel void @aliasinfo_v4f32_3v4i8_NA(ptr addrspace(1) noalias %ou
; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[GEP:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[IN_LOAD]], i32 [[TID]]
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[IN1_LOAD]], i32 [[TID]]
-; CHECK-NEXT: [[LOAD:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP]], align 1, !alias.scope [[META16:![0-9]+]], !noalias [[META19:![0-9]+]]
-; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 1, !alias.scope [[META23:![0-9]+]], !noalias [[META24:![0-9]+]]
+; CHECK-NEXT: [[LOAD:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP]], align 1, !alias.scope [[META16:![0-9]+]]
+; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 1, !alias.scope [[META19:![0-9]+]]
; CHECK-NEXT: [[SHUFFLE0_0:%.*]] = shufflevector <4 x i8> [[LOAD]], <4 x i8> [[LOAD1]], <4 x i32> <i32 3, i32 2, i32 6, i32 2>
; CHECK-NEXT: [[CVT:%.*]] = uitofp <4 x i8> [[SHUFFLE0_0]] to <4 x float>
-; CHECK-NEXT: store <4 x float> [[CVT]], ptr addrspace(1) [[OUT_LOAD]], align 16, !alias.scope [[META25:![0-9]+]], !noalias [[META26:![0-9]+]]
-; CHECK-NEXT: store <4 x i8> [[SHUFFLE0_0]], ptr addrspace(1) [[OUT1_LOAD]], align 4, !alias.scope [[META27:![0-9]+]], !noalias [[META28:![0-9]+]]
+; CHECK-NEXT: store <4 x float> [[CVT]], ptr addrspace(1) [[OUT_LOAD]], align 16, !alias.scope [[META21:![0-9]+]]
+; CHECK-NEXT: store <4 x i8> [[SHUFFLE0_0]], ptr addrspace(1) [[OUT1_LOAD]], align 4, !alias.scope [[META23:![0-9]+]]
; CHECK-NEXT: ret void
;
entry:
@@ -228,12 +228,12 @@ define amdgpu_kernel void @aliasinfo_v4f32_3v4i8_NA_AS(ptr addrspace(1) noalias
; CHECK-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[GEP:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[IN_LOAD]], i32 [[TID]]
; CHECK-NEXT: [[GEP1:%.*]] = getelementptr <4 x i8>, ptr addrspace(1) [[IN1_LOAD]], i32 [[TID]]
-; CHECK-NEXT: [[LOAD:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP]], align 1, !alias.scope [[META29:![0-9]+]], !noalias [[META32:![0-9]+]]
-; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 1, !alias.scope [[META36:![0-9]+]], !noalias [[META37:![0-9]+]]
+; CHECK-NEXT: [[LOAD:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP]], align 1, !alias.scope [[META25:![0-9]+]], !noalias [[META9]]
+; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i8>, ptr addrspace(1) [[GEP1]], align 1, !alias.scope [[META28:![0-9]+]], !noalias [[META9]]
; CHECK-NEXT: [[SHUFFLE0_0:%.*]] = shufflevector <4 x i8> [[LOAD]], <4 x i8> [[LOAD1]], <4 x i32> <i32 3, i32 2, i32 6, i32 2>
; CHECK-NEXT: [[CVT:%.*]] = uitofp <4 x i8> [[SHUFFLE0_0]] to <4 x float>
-; CHECK-NEXT: store <4 x float> [[CVT]], ptr addrspace(1) [[OUT_LOAD]], align 16, !alias.scope [[META38:![0-9]+]], !noalias [[META39:![0-9]+]]
-; CHECK-NEXT: store <4 x i8> [[SHUFFLE0_0]], ptr addrspace(1) [[OUT1_LOAD]], align 4, !alias.scope [[META40:![0-9]+]], !noalias [[META41:![0-9]+]]
+; CHECK-NEXT: store <4 x float> [[CVT]], ptr addrspace(1) [[OUT_LOAD]], align 16, !alias.scope [[META30:![0-9]+]], !noalias [[META6]]
+; CHECK-NEXT: store <4 x i8> [[SHUFFLE0_0]], ptr addrspace(1) [[OUT1_LOAD]], align 4, !alias.scope [[META32:![0-9]+]], !noalias [[META6]]
; CHECK-NEXT: ret void
;
entry:
@@ -287,11 +287,11 @@ define amdgpu_kernel void @aliasinfo_mixed_intrinsics_NA(ptr addrspace(1) noalia
; CHECK-NEXT: [[INOUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[INOUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_MIXED_INTRINSICS_NA_KERNARG_SEGMENT]], i64 52
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: [[VAL1:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[IN_LOAD]]), !noalias [[META42:![0-9]+]]
-; CHECK-NEXT: [[VAL2:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[INOUT_LOAD]]), !noalias [[META46:![0-9]+]]
-; CHECK-NEXT: call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) [[OUT_LOAD]], ptr addrspace(1) [[INOUT_LOAD]], i64 16, i1 false), !alias.scope [[META42]], !noalias [[META47:![0-9]+]]
+; CHECK-NEXT: [[VAL1:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[IN_LOAD]]), !noalias [[META34:![0-9]+]]
+; CHECK-NEXT: [[VAL2:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[INOUT_LOAD]]), !noalias [[META38:![0-9]+]]
+; CHECK-NEXT: call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) [[OUT_LOAD]], ptr addrspace(1) [[INOUT_LOAD]], i64 16, i1 false), !alias.scope [[META34]]
; CHECK-NEXT: [[VAL3:%.*]] = fmul <4 x float> [[VAL1]], [[VAL2]]
-; CHECK-NEXT: store <4 x float> [[VAL3]], ptr addrspace(1) [[INOUT_LOAD]], align 16, !alias.scope [[META49:![0-9]+]], !noalias [[META50:![0-9]+]]
+; CHECK-NEXT: store <4 x float> [[VAL3]], ptr addrspace(1) [[INOUT_LOAD]], align 16, !alias.scope [[META39:![0-9]+]]
; CHECK-NEXT: ret void
;
entry:
@@ -341,11 +341,11 @@ define amdgpu_kernel void @aliasinfo_mixed_intrinsics_NA_AS(ptr addrspace(1) noa
; CHECK-NEXT: [[INOUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[INOUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_MIXED_INTRINSICS_NA_AS_KERNARG_SEGMENT]], i64 52
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: [[VAL1:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[IN_LOAD]]), !alias.scope [[META6]], !noalias [[META51:![0-9]+]]
-; CHECK-NEXT: [[VAL2:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[INOUT_LOAD]]), !alias.scope [[META6]], !noalias [[META55:![0-9]+]]
-; CHECK-NEXT: call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) [[OUT_LOAD]], ptr addrspace(1) [[INOUT_LOAD]], i64 16, i1 false), !alias.scope [[META51]], !noalias [[META56:![0-9]+]]
+; CHECK-NEXT: [[VAL1:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[IN_LOAD]]), !alias.scope [[META6]], !noalias [[META40:![0-9]+]]
+; CHECK-NEXT: [[VAL2:%.*]] = call <4 x float> @llvm.amdgcn.global.load.tr.b256.v4f32.p1(ptr addrspace(1) [[INOUT_LOAD]]), !alias.scope [[META6]], !noalias [[META44:![0-9]+]]
+; CHECK-NEXT: call void @llvm.memcpy.p1.p1.i64(ptr addrspace(1) [[OUT_LOAD]], ptr addrspace(1) [[INOUT_LOAD]], i64 16, i1 false), !alias.scope [[META40]], !noalias [[META6]]
; CHECK-NEXT: [[VAL3:%.*]] = fmul <4 x float> [[VAL1]], [[VAL2]]
-; CHECK-NEXT: store <4 x float> [[VAL3]], ptr addrspace(1) [[INOUT_LOAD]], align 16, !alias.scope [[META58:![0-9]+]], !noalias [[META59:![0-9]+]]
+; CHECK-NEXT: store <4 x float> [[VAL3]], ptr addrspace(1) [[INOUT_LOAD]], align 16, !alias.scope [[META45:![0-9]+]], !noalias [[META6]]
; CHECK-NEXT: ret void
;
entry:
@@ -368,10 +368,10 @@ define amdgpu_kernel void @aliasinfo_captured_before_call(ptr addrspace(1) noali
; CHECK-NEXT: [[P_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[P_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_CAPTURED_BEFORE_CALL_KERNARG_SEGMENT]], i64 44
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META60:![0-9]+]]
+; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META46:![0-9]+]]
; CHECK-NEXT: call void @readwrite_no_ptr_args()
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META60]]
-; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META60]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META46]]
+; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META46]]
; CHECK-NEXT: ret void
;
store ptr addrspace(1) %p, ptr addrspace(3) @cap
@@ -390,10 +390,10 @@ define amdgpu_kernel void @aliasinfo_captured_before_call_ptr_arg(ptr addrspace(
; CHECK-NEXT: [[P_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[P_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_CAPTURED_BEFORE_CALL_PTR_ARG_KERNARG_SEGMENT]], i64 44
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META63:![0-9]+]]
+; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META49:![0-9]+]]
; CHECK-NEXT: call void @readwrite_with_ptr_arg(ptr addrspace(1) [[OUT_LOAD]])
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META63]]
-; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META63]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META49]]
+; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META49]]
; CHECK-NEXT: ret void
;
store ptr addrspace(1) %p, ptr addrspace(3) @cap
@@ -412,10 +412,10 @@ define amdgpu_kernel void @aliasinfo_captured_after_call(ptr addrspace(1) noalia
; CHECK-NEXT: [[P_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[P_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_CAPTURED_AFTER_CALL_KERNARG_SEGMENT]], i64 44
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META66:![0-9]+]]
-; CHECK-NEXT: call void @readwrite_no_ptr_args(), !noalias [[META66]]
-; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META66]]
-; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META66]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META52:![0-9]+]]
+; CHECK-NEXT: call void @readwrite_no_ptr_args(), !noalias [[META52]]
+; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META52]]
+; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META52]]
; CHECK-NEXT: ret void
;
%v = load i32, ptr addrspace(1) %p
@@ -434,10 +434,10 @@ define amdgpu_kernel void @aliasinfo_captured_before_argmemonly_call(ptr addrspa
; CHECK-NEXT: [[P_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[P_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_CAPTURED_BEFORE_ARGMEMONLY_CALL_KERNARG_SEGMENT]], i64 44
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META69:![0-9]+]]
-; CHECK-NEXT: call void @argmemonly_rw_with_ptr_arg(ptr addrspace(1) [[OUT_LOAD]]), !noalias [[META69]]
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META69]]
-; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META69]]
+; CHECK-NEXT: store ptr addrspace(1) [[P_LOAD]], ptr addrspace(3) @cap, align 8, !noalias [[META55:![0-9]+]]
+; CHECK-NEXT: call void @argmemonly_rw_with_ptr_arg(ptr addrspace(1) [[OUT_LOAD]]), !noalias [[META55]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META55]]
+; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META55]]
; CHECK-NEXT: ret void
;
store ptr addrspace(1) %p, ptr addrspace(3) @cap
@@ -458,9 +458,9 @@ define amdgpu_kernel void @aliasinfo_no_scope_on_nonargmem_call(ptr addrspace(1)
; CHECK-NEXT: [[Q_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[Q_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_NO_SCOPE_ON_NONARGMEM_CALL_KERNARG_SEGMENT]], i64 52
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
-; CHECK-NEXT: call void @readwrite_with_ptr_arg(ptr addrspace(1) [[P_LOAD]]), !noalias [[META72:![0-9]+]]
-; CHECK-NEXT: [[W:%.*]] = load i32, ptr addrspace(1) [[Q_LOAD]], align 4, !alias.scope [[META72]], !noalias [[META75:![0-9]+]]
-; CHECK-NEXT: store i32 [[W]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META77:![0-9]+]]
+; CHECK-NEXT: call void @readwrite_with_ptr_arg(ptr addrspace(1) [[P_LOAD]]), !noalias [[META58:![0-9]+]]
+; CHECK-NEXT: [[W:%.*]] = load i32, ptr addrspace(1) [[Q_LOAD]], align 4, !alias.scope [[META58]]
+; CHECK-NEXT: store i32 [[W]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META61:![0-9]+]]
; CHECK-NEXT: ret void
;
call void @readwrite_with_ptr_arg(ptr addrspace(1) %p)
@@ -479,8 +479,8 @@ define amdgpu_kernel void @aliasinfo_inaccessiblemem_call(ptr addrspace(1) noali
; CHECK-NEXT: [[OUT_KERNARG_OFFSET:%.*]] = getelementptr inbounds i8, ptr addrspace(4) [[ALIASINFO_INACCESSIBLEMEM_CALL_KERNARG_SEGMENT]], i64 44
; CHECK-NEXT: [[OUT_LOAD:%.*]] = load ptr addrspace(1), ptr addrspace(4) [[OUT_KERNARG_OFFSET]], align 4, !invariant.load [[META0]]
; CHECK-NEXT: call void @inaccessible_only()
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META78:![0-9]+]]
-; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META78]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META63:![0-9]+]]
+; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META63]]
; CHECK-NEXT: ret void
;
call void @inaccessible_only()
@@ -511,8 +511,8 @@ define amdgpu_kernel void @aliasinfo_unknown_object_deep_gep(ptr addrspace(1) no
; CHECK-NEXT: [[G11:%.*]] = getelementptr i8, ptr addrspace(1) [[G10]], i64 1
; CHECK-NEXT: [[GBACK:%.*]] = getelementptr i8, ptr addrspace(1) [[G11]], i64 -11
; CHECK-NEXT: store i32 42, ptr addrspace(1) [[GBACK]], align 4
-; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META81:![0-9]+]]
-; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META81]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr addrspace(1) [[P_LOAD]], align 4, !alias.scope [[META66:![0-9]+]]
+; CHECK-NEXT: store i32 [[V]], ptr addrspace(1) [[OUT_LOAD]], align 4, !noalias [[META66]]
; CHECK-NEXT: ret void
;
%g1 = getelementptr i8, ptr addrspace(1) %p, i64 1
@@ -556,7 +556,7 @@ attributes #4 = { nounwind memory(inaccessiblemem: readwrite) }
; CHECK: [[META0]] = !{}
; CHECK: [[META1]] = !{[[META2:![0-9]+]]}
; CHECK: [[META2]] = distinct !{[[META2]], [[META3:![0-9]+]], !"in"}
-; CHECK: [[META3]] = distinct !{[[META3]], i1 false, !"aliasinfo_2i32_NA"}
+; CHECK: [[META3]] = distinct !{[[META3]], i1 true, !"aliasinfo_2i32_NA"}
; CHECK: [[META4]] = !{[[META5:![0-9]+]]}
; CHECK: [[META5]] = distinct !{[[META5]], [[META3]], !"out"}
; CHECK: [[META6]] = !{[[META7:![0-9]+]]}
@@ -566,75 +566,60 @@ attributes #4 = { nounwind memory(inaccessiblemem: readwrite) }
; CHECK: [[META10]] = distinct !{[[META10]], [[META8]], !"alias_scope_1"}
; CHECK: [[META11]] = !{[[META7]], [[META12:![0-9]+]]}
; CHECK: [[META12]] = distinct !{[[META12]], [[META13:![0-9]+]], !"in"}
-; CHECK: [[META13]] = distinct !{[[META13]], i1 false, !"aliasinfo_2i32_NA_AS"}
+; CHECK: [[META13]] = distinct !{[[META13]], i1 true, !"aliasinfo_2i32_NA_AS"}
; CHECK: [[META14]] = !{[[META10]], [[META15:![0-9]+]]}
; CHECK: [[META15]] = distinct !{[[META15]], [[META13]], !"out"}
; CHECK: [[META16]] = !{[[META17:![0-9]+]]}
; CHECK: [[META17]] = distinct !{[[META17]], [[META18:![0-9]+]], !"in"}
-; CHECK: [[META18]] = distinct !{[[META18]], i1 false, !"aliasinfo_v4f32_3v4i8_NA"}
-; CHECK: [[META19]] = !{[[META20:![0-9]+]], [[META21:![0-9]+]], [[META22:![0-9]+]]}
-; CHECK: [[META20]] = distinct !{[[META20]], [[META18]], !"out"}
-; CHECK: [[META21]] = distinct !{[[META21]], [[META18]], !"out1"}
-; CHECK: [[META22]] = distinct !{[[META22]], [[META18]], !"in1"}
-; CHECK: [[META23]] = !{[[META22]]}
-; CHECK: [[META24]] = !{[[META20]], [[META21]], [[META17]]}
-; CHECK: [[META25]] = !{[[META20]]}
-; CHECK: [[META26]] = !{[[META21]], [[META17]], [[META22]]}
-; CHECK: [[META27]] = !{[[META21]]}
-; CHECK: [[META28]] = !{[[META20]], [[META17]], [[META22]]}
-; CHECK: [[META29]] = !{[[META7]], [[META30:![0-9]+]]}
-; CHECK: [[META30]] = distinct !{[[META30]], [[META31:![0-9]+]], !"in"}
-; CHECK: [[META31]] = distinct !{[[META31]], i1 false, !"aliasinfo_v4f32_3v4i8_NA_AS"}
-; CHECK: [[META32]] = !{[[META10]], [[META33:![0-9]+]], [[META34:![0-9]+]], [[META35:![0-9]+]]}
-; CHECK: [[META33]] = distinct !{[[META33]], [[META31]], !"out"}
-; CHECK: [[META34]] = distinct !{[[META34]], [[META31]], !"out1"}
-; CHECK: [[META35]] = distinct !{[[META35]], [[META31]], !"in1"}
-; CHECK: [[META36]] = !{[[META7]], [[META35]]}
-; CHECK: [[META37]] = !{[[META10]], [[META33]], [[META34]], [[META30]]}
-; CHECK: [[META38]] = !{[[META10]], [[META33]]}
-; CHECK: [[META39]] = !{[[META7]], [[META34]], [[META30]], [[META35]]}
-; CHECK: [[META40]] = !{[[META10]], [[META34]]}
-; CHECK: [[META41]] = !{[[META7]], [[META33]], [[META30]], [[META35]]}
-; CHECK: [[META42]] = !{[[META43:![0-9]+]], [[META45:![0-9]+]]}
-; CHECK: [[META43]] = distinct !{[[META43]], [[META44:![0-9]+]], !"inout"}
-; CHECK: [[META44]] = distinct !{[[META44]], i1 false, !"aliasinfo_mixed_intrinsics_NA"}
-; CHECK: [[META45]] = distinct !{[[META45]], [[META44]], !"out"}
-; CHECK: [[META46]] = !{[[META45]]}
-; CHECK: [[META47]] = !{[[META48:![0-9]+]]}
-; CHECK: [[META48]] = distinct !{[[META48]], [[META44]], !"in"}
-; CHECK: [[META49]] = !{[[META43]]}
-; CHECK: [[META50]] = !{[[META48]], [[META45]]}
-; CHECK: [[META51]] = !{[[META10]], [[META52:![0-9]+]], [[META54:![0-9]+]]}
-; CHECK: [[META52]] = distinct !{[[META52]], [[META53:![0-9]+]], !"inout"}
-; CHECK: [[META53]] = distinct !{[[META53]], i1 false, !"aliasinfo_mixed_intrinsics_NA_AS"}
-; CHECK: [[META54]] = distinct !{[[META54]], [[META53]], !"out"}
-; CHECK: [[META55]] = !{[[META10]], [[META54]]}
-; CHECK: [[META56]] = !{[[META7]], [[META57:![0-9]+]]}
-; CHECK: [[META57]] = distinct !{[[META57]], [[META53]], !"in"}
-; CHECK: [[META58]] = !{[[META10]], [[META52]]}
-; CHECK: [[META59]] = !{[[META7]], [[META57]], [[META54]]}
-; CHECK: [[META60]] = !{[[META61:![0-9]+]]}
-; CHECK: [[META61]] = distinct !{[[META61]], [[META62:![0-9]+]], !"p"}
-; CHECK: [[META62]] = distinct !{[[META62]], i1 false, !"aliasinfo_captured_before_call"}
+; CHECK: [[META18]] = distinct !{[[META18]], i1 true, !"aliasinfo_v4f32_3v4i8_NA"}
+; CHECK: [[META19]] = !{[[META20:![0-9]+]]}
+; CHECK: [[META20]] = distinct !{[[META20]], [[META18]], !"in1"}
+; CHECK: [[META21]] = !{[[META22:![0-9]+]]}
+; CHECK: [[META22]] = distinct !{[[META22]], [[META18]], !"out"}
+; CHECK: [[META23]] = !{[[META24:![0-9]+]]}
+; CHECK: [[META24]] = distinct !{[[META24]], [[META18]], !"out1"}
+; CHECK: [[META25]] = !{[[META7]], [[META26:![0-9]+]]}
+; CHECK: [[META26]] = distinct !{[[META26]], [[META27:![0-9]+]], !"in"}
+; CHECK: [[META27]] = distinct !{[[META27]], i1 true, !"aliasinfo_v4f32_3v4i8_NA_AS"}
+; CHECK: [[META28]] = !{[[META7]], [[META29:![0-9]+]]}
+; CHECK: [[META29]] = distinct !{[[META29]], [[META27]], !"in1"}
+; CHECK: [[META30]] = !{[[META10]], [[META31:![0-9]+]]}
+; CHECK: [[META31]] = distinct !{[[META31]], [[META27]], !"out"}
+; CHECK: [[META32]] = !{[[META10]], [[META33:![0-9]+]]}
+; CHECK: [[META33]] = distinct !{[[META33]], [[META27]], !"out1"}
+; CHECK: [[META34]] = !{[[META35:![0-9]+]], [[META37:![0-9]+]]}
+; CHECK: [[META35]] = distinct !{[[META35]], [[META36:![0-9]+]], !"inout"}
+; CHECK: [[META36]] = distinct !{[[META36]], i1 true, !"aliasinfo_mixed_intrinsics_NA"}
+; CHECK: [[META37]] = distinct !{[[META37]], [[META36]], !"out"}
+; CHECK: [[META38]] = !{[[META37]]}
+; CHECK: [[META39]] = !{[[META35]]}
+; CHECK: [[META40]] = !{[[META10]], [[META41:![0-9]+]], [[META43:![0-9]+]]}
+; CHECK: [[META41]] = distinct !{[[META41]], [[META42:![0-9]+]], !"inout"}
+; CHECK: [[META42]] = distinct !{[[META42]], i1 true, !"aliasinfo_mixed_intrinsics_NA_AS"}
+; CHECK: [[META43]] = distinct !{[[META43]], [[META42]], !"out"}
+; CHECK: [[META44]] = !{[[META10]], [[META43]]}
+; CHECK: [[META45]] = !{[[META10]], [[META41]]}
+; CHECK: [[META46]] = !{[[META47:![0-9]+]]}
+; CHECK: [[META47]] = distinct !{[[META47]], [[META48:![0-9]+]], !"p"}
+; CHECK: [[META48]] = distinct !{[[META48]], i1 true, !"aliasinfo_captured_before_call"}
+; CHECK: [[META49]] = !{[[META50:![0-9]+]]}
+; CHECK: [[META50]] = distinct !{[[META50]], [[META51:![0-9]+]], !"p"}
+; CHECK: [[META51]] = distinct !{[[META51]], i1 true, !"aliasinfo_captured_before_call_ptr_arg"}
+; CHECK: [[META52]] = !{[[META53:![0-9]+]]}
+; CHECK: [[META53]] = distinct !{[[META53]], [[META54:![0-9]+]], !"p"}
+; CHECK: [[META54]] = distinct !{[[META54]], i1 true, !"aliasinfo_captured_after_call"}
+; CHECK: [[META55]] = !{[[META56:![0-9]+]]}
+; CHECK: [[META56]] = distinct !{[[META56]], [[META57:![0-9]+]], !"p"}
+; CHECK: [[META57]] = distinct !{[[META57]], i1 true, !"aliasinfo_captured_before_argmemonly_call"}
+; CHECK: [[META58]] = !{[[META59:![0-9]+]]}
+; CHECK: [[META59]] = distinct !{[[META59]], [[META60:![0-9]+]], !"q"}
+; CHECK: [[META60]] = distinct !{[[META60]], i1 true, !"aliasinfo_no_scope_on_nonargmem_call"}
+; CHECK: [[META61]] = !{[[META62:![0-9]+]], [[META59]]}
+; CHECK: [[META62]] = distinct !{[[META62]], [[META60]], !"p"}
; CHECK: [[META63]] = !{[[META64:![0-9]+]]}
; CHECK: [[META64]] = distinct !{[[META64]], [[META65:![0-9]+]], !"p"}
-; CHECK: [[META65]] = distinct !{[[META65]], i1 false, !"aliasinfo_captured_before_call_ptr_arg"}
+; CHECK: [[META65]] = distinct !{[[META65]], i1 true, !"aliasinfo_inaccessiblemem_call"}
; CHECK: [[META66]] = !{[[META67:![0-9]+]]}
; CHECK: [[META67]] = distinct !{[[META67]], [[META68:![0-9]+]], !"p"}
-; CHECK: [[META68]] = distinct !{[[META68]], i1 false, !"aliasinfo_captured_after_call"}
-; CHECK: [[META69]] = !{[[META70:![0-9]+]]}
-; CHECK: [[META70]] = distinct !{[[META70]], [[META71:![0-9]+]], !"p"}
-; CHECK: [[META71]] = distinct !{[[META71]], i1 false, !"aliasinfo_captured_before_argmemonly_call"}
-; CHECK: [[META72]] = !{[[META73:![0-9]+]]}
-; CHECK: [[META73]] = distinct !{[[META73]], [[META74:![0-9]+]], !"q"}
-; CHECK: [[META74]] = distinct !{[[META74]], i1 false, !"aliasinfo_no_scope_on_nonargmem_call"}
-; CHECK: [[META75]] = !{[[META76:![0-9]+]]}
-; CHECK: [[META76]] = distinct !{[[META76]], [[META74]], !"p"}
-; CHECK: [[META77]] = !{[[META76]], [[META73]]}
-; CHECK: [[META78]] = !{[[META79:![0-9]+]]}
-; CHECK: [[META79]] = distinct !{[[META79]], [[META80:![0-9]+]], !"p"}
-; CHECK: [[META80]] = distinct !{[[META80]], i1 false, !"aliasinfo_inaccessiblemem_call"}
-; CHECK: [[META81]] = !{[[META82:![0-9]+]]}
-; CHECK: [[META82]] = distinct !{[[META82]], [[META83:![0-9]+]], !"p"}
-; CHECK: [[META83]] = distinct !{[[META83]], i1 false, !"aliasinfo_unknown_object_deep_gep"}
+; CHECK: [[META68]] = distinct !{[[META68]], i1 true, !"aliasinfo_unknown_object_deep_gep"}
;.
diff --git a/llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll b/llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
index 40cddfb0b2dc5..d0ec4b8121d00 100644
--- a/llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-split-load-store-alias-info.ll
@@ -3,17 +3,17 @@
; This test verifies that instruction selection will propagate alias metadata
; to split loads and stores.
-; CHECK: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, align 32, !alias.scope ![[IN:[0-9]+]], !noalias ![[OUT:[0-9]+]], addrspace 3)
-; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, !alias.scope ![[IN]], !noalias ![[OUT]], addrspace 3)
-; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, align 32, !alias.scope ![[IN]], !noalias ![[OUT]], addrspace 3)
-; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, !alias.scope ![[IN]], !noalias ![[OUT]], addrspace 3)
-; CHECK: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[IN]], addrspace 3)
+; CHECK: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, align 32, !alias.scope ![[IN:[0-9]+]], !noalias ![[NOT_IN:[0-9]+]], addrspace 3)
+; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, !alias.scope ![[IN]], !noalias ![[NOT_IN]], addrspace 3)
+; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, align 32, !alias.scope ![[IN]], !noalias ![[NOT_IN]], addrspace 3)
+; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = DS_READ_B128_gfx9 {{.*}} :: (load (s128) from %{{.*}}, !alias.scope ![[IN]], !noalias ![[NOT_IN]], addrspace 3)
+; CHECK: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT:[0-9]+]], !noalias ![[NOT_OUT:[0-9]+]], addrspace 3)
; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = REG_SEQUENCE
-; CHECK-NEXT: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[IN]], addrspace 3)
+; CHECK-NEXT: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[NOT_OUT]], addrspace 3)
; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = REG_SEQUENCE
-; CHECK-NEXT: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[IN]], addrspace 3)
+; CHECK-NEXT: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[NOT_OUT]], addrspace 3)
; CHECK-NEXT: %{{[0-9]+}}:vreg_128 = REG_SEQUENCE
-; CHECK-NEXT: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[IN]], addrspace 3)
+; CHECK-NEXT: DS_WRITE_B128_gfx9 {{.*}} :: (store (s128) into %{{.*}}, !alias.scope ![[OUT]], !noalias ![[NOT_OUT]], addrspace 3)
define amdgpu_kernel void @test(ptr addrspace(3) noalias %in, ptr addrspace(3) noalias %out) {
%idx = call i32 @llvm.amdgcn.workitem.id.x()
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