[llvm-branch-commits] [llvm] CodeGen: Drop the LiveVariables parameter from convertToThreeAddress (PR #225182)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Sep 28 08:55:59 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/225182
>From 7dc42151c8273d6ee1de2119617adbdc7f73d985 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 9 Sep 2026 17:16:47 +0200
Subject: [PATCH] CodeGen: Drop the LiveVariables parameter from
convertToThreeAddress
This was used for analysis updates, but now the analysis is being
removed.
Co-authored-by: Claude (Claude-Opus-4.8)
---
llvm/include/llvm/CodeGen/TargetInstrInfo.h | 1 -
.../lib/CodeGen/TwoAddressInstructionPass.cpp | 2 +-
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 4 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 17 ----
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 3 +-
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 11 ---
llvm/lib/Target/RISCV/RISCVInstrInfo.h | 2 +-
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 11 +--
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 2 +-
llvm/lib/Target/X86/X86FixupLEAs.cpp | 2 +-
llvm/lib/Target/X86/X86InstrInfo.cpp | 84 ++++---------------
llvm/lib/Target/X86/X86InstrInfo.h | 6 +-
12 files changed, 25 insertions(+), 120 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index b013511d33313..0f36bece2c12b 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -524,7 +524,6 @@ class LLVM_ABI TargetInstrInfo : public MCInstrInfo {
/// replacing \p MI with new instructions, even though this function does not
/// remove MI.
virtual MachineInstr *convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV,
LiveIntervals *LIS) const {
return nullptr;
}
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 62c87d7360e42..ca42a046c0e64 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -795,7 +795,7 @@ bool TwoAddressInstructionImpl::convertInstTo3Addr(
MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi,
Register RegA, Register RegB, unsigned &Dist) {
MachineInstrSpan MIS(mi, MBB);
- MachineInstr *NewMI = TII->convertToThreeAddress(*mi, nullptr, LIS);
+ MachineInstr *NewMI = TII->convertToThreeAddress(*mi, LIS);
if (!NewMI)
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index d7831ace7eabc..67f3354f0fbe1 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -2366,7 +2366,7 @@ bool SIFoldOperandsImpl::tryFoldClamp(MachineInstr &MI) {
// Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac
// instruction, so we might as well convert it to the more flexible VOP3-only
// mad/fma form.
- if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
+ if (TII->convertToThreeAddress(*Def, /*LIS=*/nullptr))
Def->eraseFromParent();
return true;
@@ -2623,7 +2623,7 @@ bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) {
// Use of output modifiers forces VOP3 encoding for a VOP2 mac/fmac
// instruction, so we might as well convert it to the more flexible VOP3-only
// mad/fma form.
- if (TII->convertToThreeAddress(*Def, nullptr, nullptr))
+ if (TII->convertToThreeAddress(*Def, /*LIS=*/nullptr))
Def->eraseFromParent();
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 0346ebc254361..1aa7f49051ede 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -23,7 +23,6 @@
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCycleAnalysis.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -4351,18 +4350,6 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
return false;
}
-static void updateLiveVariables(LiveVariables *LV, MachineInstr &MI,
- MachineInstr &NewMI) {
- if (LV) {
- unsigned NumOps = MI.getNumOperands();
- for (unsigned I = 1; I < NumOps; ++I) {
- MachineOperand &Op = MI.getOperand(I);
- if (Op.isReg() && Op.isKill())
- LV->replaceKillInstruction(Op.getReg(), MI, NewMI);
- }
- }
-}
-
static unsigned getNewFMAInst(const GCNSubtarget &ST, unsigned Opc) {
switch (Opc) {
case AMDGPU::V_MAC_F16_e32:
@@ -4405,7 +4392,6 @@ struct SIInstrInfo::ThreeAddressUpdates {
};
MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV,
LiveIntervals *LIS) const {
MachineBasicBlock &MBB = *MI.getParent();
MachineInstr *CandidateMI = &MI;
@@ -4431,7 +4417,6 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
MI.untieRegOperand(MO.getOperandNo());
}
} else {
- updateLiveVariables(LV, MI, *NewMI);
if (LIS) {
LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
// SlotIndex of defs needs to be updated when converting to early-clobber
@@ -4467,8 +4452,6 @@ MachineInstr *SIInstrInfo::convertToThreeAddress(MachineInstr &MI,
U.RemoveMIUse->getOperand(0).setIsDead(true);
for (unsigned I = U.RemoveMIUse->getNumOperands() - 1; I != 0; --I)
U.RemoveMIUse->removeOperand(I);
- if (LV)
- LV->getVarInfo(DefReg).AliveBlocks.clear();
}
if (MI.isBundle()) {
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 48eba6b2a567d..851b58be1fd88 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -30,7 +30,6 @@ namespace llvm {
class APInt;
class GCNSubtarget;
-class LiveVariables;
class MachineDominatorTree;
class MachineRegisterInfo;
class RegScavenger;
@@ -486,7 +485,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
unsigned getMachineCSELookAheadLimit() const override { return 500; }
- MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ MachineInstr *convertToThreeAddress(MachineInstr &MI,
LiveIntervals *LIS) const override;
bool isSchedulingBoundary(const MachineInstr &MI,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index e7aaeb0ac9e97..c9bc576b16139 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -22,7 +22,6 @@
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/LiveIntervals.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineCombinerPattern.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -5019,7 +5018,6 @@ bool RISCVInstrInfo::simplifyInstruction(MachineInstr &MI) const {
// clang-format on
MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV,
LiveIntervals *LIS) const {
MachineInstrBuilder MIB;
switch (MI.getOpcode()) {
@@ -5097,15 +5095,6 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
}
MIB.copyImplicitOps(MI);
- if (LV) {
- unsigned NumOps = MI.getNumOperands();
- for (unsigned I = 1; I < NumOps; ++I) {
- MachineOperand &Op = MI.getOperand(I);
- if (Op.isReg() && Op.isKill())
- LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
- }
- }
-
if (LIS) {
SlotIndex Idx = LIS->ReplaceMachineInstrInMaps(MI, *MIB);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index 40151c5354a22..8e47b0e0aff0b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -279,7 +279,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
bool simplifyInstruction(MachineInstr &MI) const override;
- MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ MachineInstr *convertToThreeAddress(MachineInstr &MI,
LiveIntervals *LIS) const override;
// MIR printer helper function to annotate Operands with a comment.
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bfffa39117443..e723ddb45ac55 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -19,7 +19,6 @@
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveRegUnits.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
@@ -1083,7 +1082,7 @@ static void transferMIFlag(MachineInstr *OldMI, MachineInstr *NewMI,
}
MachineInstr *
-SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI,
LiveIntervals *LIS) const {
MachineBasicBlock *MBB = MI.getParent();
@@ -1117,14 +1116,6 @@ SystemZInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
.addImm(Start)
.addImm(End + 128)
.addImm(0);
- if (LV) {
- unsigned NumOps = MI.getNumOperands();
- for (unsigned I = 1; I < NumOps; ++I) {
- MachineOperand &Op = MI.getOperand(I);
- if (Op.isReg() && Op.isKill())
- LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
- }
- }
if (LIS)
LIS->ReplaceMachineInstrInMaps(MI, *MIB);
transferDeadCC(&MI, MIB);
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 452671443bb12..a841a9667deb7 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -283,7 +283,7 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
Register DestReg, int FrameIdx, const TargetRegisterClass *RC,
Register VReg, unsigned SubReg = 0,
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
- MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ MachineInstr *convertToThreeAddress(MachineInstr &MI,
LiveIntervals *LIS) const override;
bool useMachineCombiner() const override { return true; }
diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp
index 5c9c74e64aa73..3a4b6d02030b7 100644
--- a/llvm/lib/Target/X86/X86FixupLEAs.cpp
+++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp
@@ -217,7 +217,7 @@ FixupLEAsImpl::postRAConvertToLEA(MachineBasicBlock &MBB,
// These instructions are all fine to convert.
break;
}
- return TII->convertToThreeAddress(MI, nullptr, nullptr);
+ return TII->convertToThreeAddress(MI, /*LIS=*/nullptr);
}
FunctionPass *llvm::createX86FixupLEAsLegacyPass() {
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 6fb5a4866dc13..e8c33426a3ee6 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -21,7 +21,6 @@
#include "llvm/ADT/Sequence.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LivePhysRegs.h"
-#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
@@ -1157,7 +1156,7 @@ findRedundantFlagInstr(MachineInstr &CmpInstr, MachineInstr &CmpValDefInstr,
bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
unsigned Opc, bool AllowSP, Register &NewSrc,
unsigned &NewSrcSubReg, bool &isKill,
- MachineOperand &ImplicitOp, LiveVariables *LV,
+ MachineOperand &ImplicitOp,
LiveIntervals *LIS) const {
MachineFunction &MF = *MI.getParent()->getParent();
const TargetRegisterClass *RC;
@@ -1208,9 +1207,6 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
// Which is obviously going to be dead after we're done with it.
isKill = true;
- if (LV)
- LV->replaceKillInstruction(SrcReg, MI, *Copy);
-
if (LIS) {
SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy);
SlotIndex Idx = LIS->getInstructionIndex(MI);
@@ -1227,7 +1223,6 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
MachineInstr &MI,
- LiveVariables *LV,
LiveIntervals *LIS,
bool Is8BitOp) const {
// We handle 8-bit adds and various 16-bit opcodes in the switch below.
@@ -1339,8 +1334,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
addRegReg(MIB, InRegLEA, true, X86::NoSubRegister, InRegLEA2, true,
X86::NoSubRegister);
}
- if (LV && IsKill2 && InsMI2)
- LV->replaceKillInstruction(Src2, MI, *InsMI2);
break;
}
}
@@ -1351,18 +1344,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
.addReg(Dest, RegState::Define | getDeadRegState(IsDead))
.addReg(OutRegLEA, RegState::Kill, SubReg);
- if (LV) {
- // Update live variables.
- LV->getVarInfo(InRegLEA).Kills.push_back(NewMI);
- if (InRegLEA2)
- LV->getVarInfo(InRegLEA2).Kills.push_back(NewMI);
- LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI);
- if (IsKill)
- LV->replaceKillInstruction(Src, MI, *InsMI);
- if (IsDead)
- LV->replaceKillInstruction(Dest, MI, *ExtMI);
- }
-
if (LIS) {
LIS->InsertMachineInstrInMaps(*ImpDef);
SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI);
@@ -1420,7 +1401,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
/// performed, otherwise it returns the new instruction.
///
MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
- LiveVariables *LV,
LiveIntervals *LIS) const {
// The following opcodes also sets the condition code register(s). Only
// convert them to equivalent lea if the condition code register def's
@@ -1449,7 +1429,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool Is64Bit = Subtarget.is64Bit();
bool Is8BitOp = false;
- unsigned NumRegOperands = 2;
unsigned MIOpc = MI.getOpcode();
switch (MIOpc) {
default:
@@ -1486,7 +1465,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool isKill;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, SrcSubReg,
- isKill, ImplicitOp, LV, LIS))
+ isKill, ImplicitOp, LIS))
return nullptr;
MachineInstrBuilder MIB =
@@ -1501,9 +1480,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
MIB.add(ImplicitOp);
NewMI = MIB;
- // Add kills if classifyLEAReg created a new register.
- if (LV && SrcReg != Src.getReg())
- LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
CASE_NF(SHL8ri)
@@ -1514,7 +1490,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
if (!isTruncatedShiftCountForLEA(ShAmt))
return nullptr;
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
+ return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
}
CASE_NF(INC64r)
CASE_NF(INC32r) {
@@ -1525,7 +1501,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool isKill;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, SrcSubReg,
- isKill, ImplicitOp, LV, LIS))
+ isKill, ImplicitOp, LIS))
return nullptr;
MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
@@ -1536,9 +1512,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
NewMI = addOffset(MIB, 1);
- // Add kills if classifyLEAReg created a new register.
- if (LV && SrcReg != Src.getReg())
- LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
CASE_NF(DEC64r)
@@ -1551,7 +1524,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool isKill;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, SrcSubReg,
- isKill, ImplicitOp, LV, LIS))
+ isKill, ImplicitOp, LIS))
return nullptr;
MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
@@ -1562,9 +1535,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
NewMI = addOffset(MIB, -1);
- // Add kills if classifyLEAReg created a new register.
- if (LV && SrcReg != Src.getReg())
- LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
CASE_NF(DEC8r)
@@ -1573,7 +1543,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
[[fallthrough]];
CASE_NF(DEC16r)
CASE_NF(INC16r)
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
+ return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
CASE_NF(ADD64rr)
CASE_NF(ADD32rr)
case X86::ADD64rr_DB:
@@ -1590,7 +1560,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool isKill2;
MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/false, SrcReg2, SrcSubReg2,
- isKill2, ImplicitOp2, LV, LIS))
+ isKill2, ImplicitOp2, LIS))
return nullptr;
bool isKill;
@@ -1603,7 +1573,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
SrcSubReg = SrcSubReg2;
} else {
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, SrcSubReg,
- isKill, ImplicitOp, LV, LIS))
+ isKill, ImplicitOp, LIS))
return nullptr;
}
@@ -1616,14 +1586,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
NewMI =
addRegReg(MIB, SrcReg, isKill, SrcSubReg, SrcReg2, isKill2, SrcSubReg2);
- // Add kills if classifyLEAReg created a new register.
- if (LV) {
- if (SrcReg2 != Src2.getReg())
- LV->getVarInfo(SrcReg2).Kills.push_back(NewMI);
- if (SrcReg != SrcReg2 && SrcReg != Src.getReg())
- LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
- }
- NumRegOperands = 3;
break;
}
CASE_NF(ADD8rr)
@@ -1632,8 +1594,8 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
[[fallthrough]];
CASE_NF(ADD16rr)
case X86::ADD16rr_DB:
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
- CASE_NF(ADD64ri32)
+ return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
+ CASE_NF(ADD64ri32)
case X86::ADD64ri32_DB:
assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
NewMI = addOffset(
@@ -1648,7 +1610,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool isKill;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, SrcSubReg,
- isKill, ImplicitOp, LV, LIS))
+ isKill, ImplicitOp, LIS))
return nullptr;
MachineInstrBuilder MIB =
@@ -1660,9 +1622,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
NewMI = addOffset(MIB, MI.getOperand(2));
- // Add kills if classifyLEAReg created a new register.
- if (LV && SrcReg != Src.getReg())
- LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
CASE_NF(ADD8ri)
@@ -1671,9 +1630,9 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
[[fallthrough]];
CASE_NF(ADD16ri)
case X86::ADD16ri_DB:
- return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
- CASE_NF(SUB8ri)
- CASE_NF(SUB16ri)
+ return convertToThreeAddressWithLEA(MIOpc, MI, LIS, Is8BitOp);
+ CASE_NF(SUB8ri)
+ CASE_NF(SUB16ri)
/// FIXME: Support these similar to ADD8ri/ADD16ri*.
return nullptr;
CASE_NF(SUB32ri) {
@@ -1689,7 +1648,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
bool isKill;
MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, SrcSubReg,
- isKill, ImplicitOp, LV, LIS))
+ isKill, ImplicitOp, LIS))
return nullptr;
MachineInstrBuilder MIB =
@@ -1701,9 +1660,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
NewMI = addOffset(MIB, -Imm);
- // Add kills if classifyLEAReg created a new register.
- if (LV && SrcReg != Src.getReg())
- LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
break;
}
@@ -1901,7 +1857,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
.add(MI.getOperand(5))
.add(MI.getOperand(6))
.add(MI.getOperand(7));
- NumRegOperands = 4;
break;
}
@@ -2036,7 +1991,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
.add(MI.getOperand(2))
.add(Src)
.add(MI.getOperand(3));
- NumRegOperands = 4;
break;
}
}
@@ -2045,14 +1999,6 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
if (!NewMI)
return nullptr;
- if (LV) { // Update live variables
- for (unsigned I = 0; I < NumRegOperands; ++I) {
- MachineOperand &Op = MI.getOperand(I);
- if (Op.isReg() && (Op.isDead() || Op.isKill()))
- LV->replaceKillInstruction(Op.getReg(), MI, *NewMI);
- }
- }
-
MachineBasicBlock &MBB = *MI.getParent();
MBB.insert(MI.getIterator(), NewMI); // Insert the new inst
diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
index c018fcb124e70..fe26940f85357 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.h
+++ b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -371,8 +371,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
unsigned &NewSrcSubReg, bool &isKill,
- MachineOperand &ImplicitOp, LiveVariables *LV,
- LiveIntervals *LIS) const;
+ MachineOperand &ImplicitOp, LiveIntervals *LIS) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
@@ -384,7 +383,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
/// This method returns a null pointer if the transformation cannot be
/// performed, otherwise it returns the new instruction.
///
- MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
+ MachineInstr *convertToThreeAddress(MachineInstr &MI,
LiveIntervals *LIS) const override;
/// Returns true iff the routine could find two commutable operands in the
@@ -716,7 +715,6 @@ class X86InstrInfo final : public X86GenInstrInfo {
/// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
/// super-register and then truncating back down to a 8/16-bit sub-register.
MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
- LiveVariables *LV,
LiveIntervals *LIS,
bool Is8BitOp) const;
More information about the llvm-branch-commits
mailing list