[llvm-branch-commits] [mlir] [mlir] Migrate AMDGPU/ROCDL to targets, not chipset versions (PR #223563)

[Mehdi Amini via llvm-branch-commits]

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@@ -202,15 +135,16 @@ static Value getNumRecords(ConversionPatternRewriter &rewriter, Location loc,
 
 static Value makeBufferRsrc(ConversionPatternRewriter &rewriter, Location loc,
                             Value basePointer, Value numRecords,
-                            bool boundsCheck, amdgpu::Chipset chipset,
+                            bool boundsCheck, const ROCDL::TargetInfo &target,
+                            unsigned numRecordsWidth,
                             Value cacheSwizzleStride = nullptr,
                             unsigned addressSpace = 8) {
   // The stride value is generally 0. However, on MI-300 and onward, you can
   // enable a cache swizzling mode by setting bit 14 of the stride field
   // and setting that stride to a cache stride.
   Type i16 = rewriter.getI16Type();
   Value stride;
-  if (chipset.majorVersion == 9 && chipset >= kGfx942 && cacheSwizzleStride) {
+  if (target.has(llvm::AMDGPU::FEAT_GFX940_INSTS) && cacheSwizzleStride) {
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joker-eph wrote:

This looks like a nice readability improvement!!

https://github.com/llvm/llvm-project/pull/223563