[llvm-branch-commits] [llvm] [AMDGPU] Insert wmma coexec aware anti-hints rules (PR #226397)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-globalisel

Author: Syadus Sefat (mssefat)

<details>
<summary>Changes</summary>


This patch ports the downstream coexec anti-hint insertion to upstream as rule-based insertion in the AMDGPU pre-ra anti-hints framework. It adds gfx1250x anti-hint rules for wmma coexec hazards such as A/B source war, swmmac index war, dest waw), trans source war, memory-address war etc. Each rule builds anti-hints relationship for the register allocator to keep hazardous registers in different physical registers so the hazard recognizer and waitcnt inserter need less nop and waits.

Co-authored-by:  Jeffrey Byrnes <jrbyrnes1989@<!-- -->gmail.com>


---
Full diff: https://github.com/llvm/llvm-project/pull/226397.diff


56 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/GCNPreRAAntiHints.cpp (+257-25) 
- (modified) llvm/lib/Target/AMDGPU/GCNPreRAAntiHints.h (+22-4) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll (+24-36) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll (+10-10) 
- (modified) llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll (+12-12) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-addr-xcnt.gfx1250.mir (+497) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-multi-hazard.gfx1250.mir (+268) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-multi-rule.gfx1250.mir (+351) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-swmmac-war-index.gfx1250.mir (+54) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-trans-src0.gfx1250.mir (+166) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-va-vdst.gfx1250.mir (+137) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-wmma-war.gfx1250.mir (+1610) 
- (added) llvm/test/CodeGen/AMDGPU/anti-hints-wmma-waw.gfx1250.mir (+2293) 
- (modified) llvm/test/CodeGen/AMDGPU/anyext-s16-to-s64.ll (+3-4) 
- (modified) llvm/test/CodeGen/AMDGPU/asyncmark-gfx12plus.ll (+84-91) 
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll (+10-14) 
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll (+10-14) 
- (modified) llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll (+10-14) 
- (modified) llvm/test/CodeGen/AMDGPU/bf16.ll (+167-132) 
- (modified) llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx1250.ll (+8-10) 
- (modified) llvm/test/CodeGen/AMDGPU/carryout-selection.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/coexec-scheduler.ll (+37-42) 
- (modified) llvm/test/CodeGen/AMDGPU/ds_read2-gfx1250.ll (+1-1) 
- (modified) llvm/test/CodeGen/AMDGPU/ds_write2.ll (+15-19) 
- (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.bf16.ll (+12-12) 
- (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.ll (+3-3) 
- (modified) llvm/test/CodeGen/AMDGPU/flat-load-saddr-to-vaddr.ll (+4-4) 
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll (+193-177) 
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll (+27-33) 
- (modified) llvm/test/CodeGen/AMDGPU/fp-min-max-buffer-ptr-atomics.ll (+10-10) 
- (modified) llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll (+24-36) 
- (modified) llvm/test/CodeGen/AMDGPU/fp64-min-max-buffer-ptr-atomics.ll (+4-6) 
- (modified) llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll (+139-148) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.load.b128.ll (+148-167) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.av.store.b128.ll (+69-69) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll (+42-22) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll (+34-16) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.private.ll (+4-4) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.is.shared.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.bf16.ll (+32-36) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.gfx950.ll (+114-132) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.ll (+82-68) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load.ll (+24-20) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.bf16.ll (+18-18) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/llvm.sqrt.bf16.ll (+2-2) 
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i1.ll (+354-392) 
- (modified) llvm/test/CodeGen/AMDGPU/load-constant-i32.ll (+81-90) 
- (modified) llvm/test/CodeGen/AMDGPU/lshl-add-u64.ll (+4-4) 
- (modified) llvm/test/CodeGen/AMDGPU/max.ll (+12-12) 
- (modified) llvm/test/CodeGen/AMDGPU/min.ll (+3-4) 
- (modified) llvm/test/CodeGen/AMDGPU/pk-lshl-add-u64.ll (+12-14) 
- (modified) llvm/test/CodeGen/AMDGPU/sad.ll (+34-42) 
- (modified) llvm/test/CodeGen/AMDGPU/trans-bf16-omod.ll (+8-8) 
- (modified) llvm/test/CodeGen/AMDGPU/vopd3-imm-fold.ll (+8-8) 


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</details>


https://github.com/llvm/llvm-project/pull/226397