[llvm-branch-commits] [llvm] [RISCV] Remove getMaxLMULForFixedLengthVectors. NFC (PR #226111)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Luke Lau (lukel97)

<details>
<summary>Changes</summary>

The value can no longer be overridden after https://github.com/llvm/llvm-project/pull/207312. Now there's nothing specific about it to fixed vectors, so just inline it.

---
Full diff: https://github.com/llvm/llvm-project/pull/226111.diff


4 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+2-4) 
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.cpp (-6) 
- (modified) llvm/lib/Target/RISCV/RISCVSubtarget.h (-1) 
- (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d4ce17dd45a49..e6c94fc9fc22c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3385,7 +3385,7 @@ static bool useRVVForFixedLengthVectorVT(MVT VT,
 
   unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
   // Don't use RVV for types that don't fit.
-  if (LMul > Subtarget.getMaxLMULForFixedLengthVectors())
+  if (LMul > 8)
     return false;
 
   // TODO: Perhaps an artificial restriction, but worth having whilst getting
@@ -20248,9 +20248,7 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC,
   unsigned OpSize = OpVT.getSizeInBits();
   // The size should be larger than XLen and smaller than the maximum vector
   // size.
-  if (OpSize <= Subtarget.getXLen() ||
-      OpSize > Subtarget.getRealMinVLen() *
-                   Subtarget.getMaxLMULForFixedLengthVectors())
+  if (OpSize <= Subtarget.getXLen() || OpSize > Subtarget.getRealMinVLen() * 8)
     return SDValue();
 
   // Don't perform this combine if constructing the vector will be expensive.
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 02e9f1f412ab3..747e10152ddf6 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -261,12 +261,6 @@ unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
   return RVVVectorBitsMin;
 }
 
-unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
-  assert(hasVInstructions() &&
-         "Tried to get vector length without Zve or V extension support!");
-  return 8;
-}
-
 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
   return hasVInstructions() &&
          getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index fcb4ea2b6635b..759de71827a77 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -390,7 +390,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   unsigned getMispredictionPenalty() const override;
   unsigned getLoadLatency() const override;
 
-  unsigned getMaxLMULForFixedLengthVectors() const;
   bool useRVVForFixedLengthVectors() const;
 
   bool enableSubRegLiveness() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 72803cf735159..e168a1036bc65 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -3733,7 +3733,7 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
     // The minimum size should be `XLen / 8 + 1`, and the maxinum size should be
     // `VLenB * MaxLMUL` so that it fits in a single register group.
     unsigned MinSize = ST->getXLen() / 8 + 1;
-    unsigned MaxSize = VLenB * ST->getMaxLMULForFixedLengthVectors();
+    unsigned MaxSize = VLenB * 8;
     for (unsigned Size = MinSize; Size <= MaxSize; Size++)
       Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
   }

``````````

</details>


https://github.com/llvm/llvm-project/pull/226111