[llvm-branch-commits] [llvm] [RISC-V] Update streamer ArchString in emitTargetFeaturePush() (PR #225133)

[Alexander Richardson via llvm-branch-commits]

https://github.com/arichardson updated https://github.com/llvm/llvm-project/pull/225133

>From 697caa84ac3b8d1aacee76b0f423bf25138db172 Mon Sep 17 00:00:00 2001
From: Alex Richardson <alexrichardson at google.com>
Date: Mon, 21 Sep 2026 23:42:27 -0700
Subject: [PATCH] [RISC-V] Update streamer ArchString in
 emitTargetFeaturePush()

Previously, RISCVAsmPrinter::emitTargetFeaturePush() only emitted `.option push`
and `.option arch` without updating the streamer's active ArchString. When
emitting an ELF object file directly (`-filetype=obj`),
RISCVTargetELFStreamer::emitDirectiveOptionArch() is a no-op while
emitTargetFeaturePop() resets ArchString back to the pushed ArchString, so
module-level inline assembly and functions with custom `target-features` failed
to emit updated `$x<arch>` mapping symbols.

Call RTS.setArchString() with the parsed ISA string in emitTargetFeaturePush()
so `-filetype=obj` records the active `$x<arch>` mapping symbol alongside
`.option arch`.

This commit was created with the help of AI tools
---
 llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp            | 2 ++
 llvm/test/CodeGen/RISCV/module-asm-features.ll       | 7 ++-----
 llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll | 7 ++++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index 04da2ce2b2bfe9..9272f7abdb23c3 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -562,6 +562,8 @@ bool RISCVAsmPrinter::emitTargetFeaturePush(const MCSubtargetInfo &STI) {
   if (!NeedEmitStdOptionArgs.empty()) {
     RTS.emitDirectiveOptionPush();
     RTS.emitDirectiveOptionArch(NeedEmitStdOptionArgs);
+    RTS.setArchString(
+        cantFail(RISCVFeatures::parseFeatureBits(STI))->toString());
     return true;
   }
 
diff --git a/llvm/test/CodeGen/RISCV/module-asm-features.ll b/llvm/test/CodeGen/RISCV/module-asm-features.ll
index 7fee7188e0ed8a..87c970956a5203 100644
--- a/llvm/test/CodeGen/RISCV/module-asm-features.ll
+++ b/llvm/test/CodeGen/RISCV/module-asm-features.ll
@@ -14,14 +14,11 @@
 ; CHECK-NEXT:   ret
 ; EXTRA-FEATURES-NEXT: .option pop
 
-;; TODO: emitTargetFeaturePush does not call setArchString(), so the mapping
-;; symbol does not record +d/+f/+zicsr when assembling directly to an object
-;; file, causing llvm-objdump to fail to disassemble `fld`.
 ; OBJ-LABEL: Disassembly of section .text:
 ; OBJ-EMPTY:
-; OBJ-NEXT:  0000000000000000 <$xrv64i2p1>:
+; OBJ-NEXT:  0000000000000000 <$xrv64i2p1_f2p2_d2p2_zicsr2p0>:
 ; OBJ-NEXT:  0000000000000000 <func>:
-; OBJ-NEXT:         0:      	<unknown>
+; OBJ-NEXT:         0:      	fld	ft0, 0x0(sp)
 ; OBJ-NEXT:         4:      	ret
 ; OBJ-NOT:   {{.}}
 
diff --git a/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll b/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
index de3de8c27df1dc..61b06c605ba2a0 100644
--- a/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-func-target-feature.ll
@@ -2,20 +2,21 @@
 ; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 -filetype=obj < %s \
 ; RUN:   | llvm-objdump -d --show-all-symbols --no-show-raw-insn - | FileCheck %s --check-prefix=OBJ
 
-;; TODO: emitTargetFeaturePush does not call setArchString(), so per-function
-;; target-features are not reflected in the $x<arch> mapping symbols.
 ; OBJ-LABEL: Disassembly of section .text:
 ; OBJ-EMPTY:
-; OBJ-NEXT:  0000000000000000 <$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0>:
+; OBJ-NEXT:  0000000000000000 <$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0>:
 ; OBJ-NEXT:  0000000000000000 <test1>:
 ; OBJ-NEXT:         0:      	ret
 ; OBJ-EMPTY:
+; OBJ-NEXT:  0000000000000002 <$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zihintntl1p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0>:
 ; OBJ-NEXT:  0000000000000002 <test2>:
 ; OBJ-NEXT:         2:      	ret
 ; OBJ-EMPTY:
+; OBJ-NEXT:  0000000000000004 <$xrv64i2p1_a2p1_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0>:
 ; OBJ-NEXT:  0000000000000004 <test3>:
 ; OBJ-NEXT:         4:      	ret
 ; OBJ-EMPTY:
+; OBJ-NEXT:  0000000000000006 <$xrv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0>:
 ; OBJ-NEXT:  0000000000000006 <test4>:
 ; OBJ-NEXT:         6:      	ret
 ; OBJ-EMPTY: