[llvm-branch-commits] [llvm] [AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering (PR #224080)

[Pankaj Dwivedi via llvm-branch-commits]

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@@ -3479,8 +3486,19 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
             assert(ResultReg.isPhysical());
             NewDest = ResultReg;
           } else {
+            // Spilling an SGPR here would flip EXEC with S_NOT, and that
+            // clobbers the SCC this path exists to preserve, so scale FrameReg
+            // in place instead.
             NewDest = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
-                                                    Shift, false, 0);
+                                                    Shift, false, 0,
+                                                    /*AllowSpill=*/false);
+            if (!NewDest) {
+              if (!CanUseFrameRegAsSGPRScratch)
+                report_fatal_error("Cannot scavenge register while SCC is live "
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PankajDwivedi-25 wrote:

Nit: `emitUnsupportedError` rather than `report_fatal_error` here? It's what this file already uses for this hazard, and this is reachable from plain MIR like `S_CSELECT_B32 %stack.0, $sgpr32, implicit $scc`, so "PLEASE submit a bug report" is a bit misleading.

https://github.com/llvm/llvm-project/pull/224080