[llvm-branch-commits] [llvm] [AMDGPU] Don't spill an SGPR while SCC is live in frame index lowering (PR #224080)
Domenic Nutile via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Sep 21 14:03:32 PDT 2026
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@@ -3421,11 +3421,32 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
// Scaling FrameReg in place is the last resort when there is nothing to
// scavenge. It has to be undone after MI, which is only possible while MI
// does not use FrameReg for anything besides the frame index.
- bool CanUseFrameRegAsScratch = IsSALU && !LiveSCC && FrameReg &&
- !MI->readsRegister(FrameReg, this) &&
- !MI->modifiesRegister(FrameReg, this);
+ bool CanUseFrameRegAsSGPRScratch = IsSALU && FrameReg &&
+ !MI->readsRegister(FrameReg, this) &&
+ !MI->modifiesRegister(FrameReg, this);
+ // ResultReg is a VGPR while SCC is live, so FrameReg cannot stand in for
+ // it there.
+ bool CanUseFrameRegAsScratch = CanUseFrameRegAsSGPRScratch && !LiveSCC;
bool RestoreFrameReg = false;
+
+ // Scavenge the scalar temporary the V_READFIRSTLANE_B32 result lands in.
+ // Spilling an SGPR here would flip EXEC with S_NOT, and that clobbers the
+ // SCC this path exists to preserve, so fall back to FrameReg instead.
+ auto ScavengeSGPRForReadfirstlane =
+ [&](MachineBasicBlock::iterator To) -> Register {
+ if (Register Reg = RS->scavengeRegisterBackwards(
+ AMDGPU::SReg_32_XM0RegClass, To, false, 0,
+ /*AllowSpill=*/false))
+ return Reg;
+ if (CanUseFrameRegAsSGPRScratch) {
+ RestoreFrameReg = true;
+ return FrameReg;
+ }
+ return RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass, To,
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saxlungs wrote:
I was covering for a case that didn't need to be. Did a bit of a refactor here, no more lambda and added some error outs when there are no options left
https://github.com/llvm/llvm-project/pull/224080
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