[llvm-branch-commits] [llvm] [AMDGPU] Do not match an f16 extension as a bf16 mix source (PR #224912)
Dmitry Sidorov via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Sep 20 15:12:18 PDT 2026
https://github.com/MrSidims updated https://github.com/llvm/llvm-project/pull/224912
>From be40d5b0614d9dc6813adef16046683cbfc39f3b Mon Sep 17 00:00:00 2001
From: Dmitry Sidorov <Dmitry.Sidorov at amd.com>
Date: Sat, 19 Sep 2026 21:03:12 +0200
Subject: [PATCH] [AMDGPU] Do not match an f16 extension as a bf16 mix source
Assisted-by: Claude Code Opus 5
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 3 +-
llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll | 23 +++++--
llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll | 69 ++++++++++++++-----
3 files changed, 70 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 0d212f9dd39b2..ff58f560314ab 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -4287,7 +4287,8 @@ bool AMDGPUDAGToDAGISel::SelectVOP3PMadMixModsImpl(SDValue In, SDValue &Src,
SelectVOP3ModsImpl(In, Src, Mods);
bool IsExtractHigh = false;
- if (Src.getOpcode() == ISD::FP_EXTEND) {
+ if (Src.getOpcode() == ISD::FP_EXTEND &&
+ Src.getOperand(0).getValueType() == VT) {
Src = Src.getOperand(0);
} else if (VT == MVT::bf16) {
SDValue B16 = matchBF16FPExtendLike(Src, IsExtractHigh);
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
index b6f7c6647d868..ad9acc26dcba3 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-hi-bf16.ll
@@ -19,12 +19,23 @@ define <2 x bfloat> @v_mad_mixhi_bf16_bf16lo_bf16lo_bf16lo_undeflo(bfloat %src0,
}
define <2 x bfloat> @v_mad_mixhi_bf16_f16lo_bf16lo_bf16lo_poisonlo(half %src0, bfloat %src1, bfloat %src2) #0 {
-; GFX1250-LABEL: v_mad_mixhi_bf16_f16lo_bf16lo_bf16lo_poisonlo:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,1]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixhi_bf16_f16lo_bf16lo_bf16lo_poisonlo:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,1]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixhi_bf16_f16lo_bf16lo_bf16lo_poisonlo:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mixhi_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,1]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext bfloat %src1 to float
%src2.ext = fpext bfloat %src2 to float
diff --git a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
index ffff36787ca22..cb34b593a52dd 100644
--- a/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/mad-mix-lo-bf16.ll
@@ -71,12 +71,23 @@ define bfloat @v_mad_mixlo_bf16_bf16lo_bf16lo_f32(bfloat %src0, bfloat %src1, fl
}
define bfloat @v_mad_mixlo_bf16_f16lo_bf16lo_f32(half %src0, bfloat %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mixlo_bf16_f16lo_bf16lo_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_f16lo_bf16lo_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_f16lo_bf16lo_f32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[0,1,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext half %src0 to float
%src1.ext = fpext bfloat %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -85,12 +96,23 @@ define bfloat @v_mad_mixlo_bf16_f16lo_bf16lo_f32(half %src0, bfloat %src1, float
}
define bfloat @v_mad_mixlo_bf16_bf16lo_f16lo_f32(bfloat %src0, half %src1, float %src2) #0 {
-; GFX1250-LABEL: v_mad_mixlo_bf16_bf16lo_f16lo_f32:
-; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,0,0]
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: v_mad_mixlo_bf16_bf16lo_f16lo_f32:
+; GFX1250-FAKE16: ; %bb.0:
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_f32_f16_e32 v1, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,0,0]
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: v_mad_mixlo_bf16_bf16lo_f16lo_f32:
+; GFX1250-REAL16: ; %bb.0:
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_cvt_f32_f16_e32 v1, v1.l
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, v2 op_sel_hi:[1,0,0]
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
%src0.ext = fpext bfloat %src0 to float
%src1.ext = fpext half %src1 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2)
@@ -613,12 +635,23 @@ define bfloat @mixlo_fptrunc_neg_src_mod(float %a, float %b) #0 {
}
define bfloat @mixlo_fptrunc_f16_src(half %a, float %b) #0 {
-; GFX1250-LABEL: mixlo_fptrunc_f16_src:
-; GFX1250: ; %bb.0: ; %.entry
-; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_fma_mixlo_bf16 v0, v0, v1, neg(0)
-; GFX1250-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-FAKE16-LABEL: mixlo_fptrunc_f16_src:
+; GFX1250-FAKE16: ; %bb.0: ; %.entry
+; GFX1250-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, neg(0)
+; GFX1250-FAKE16-NEXT: s_set_pc_i64 s[30:31]
+;
+; GFX1250-REAL16-LABEL: mixlo_fptrunc_f16_src:
+; GFX1250-REAL16: ; %bb.0: ; %.entry
+; GFX1250-REAL16-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
+; GFX1250-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_fma_mixlo_bf16 v0, v0, v1, neg(0)
+; GFX1250-REAL16-NEXT: s_set_pc_i64 s[30:31]
.entry:
%a.ext = fpext half %a to float
%mul = fmul float %a.ext, %b
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