[llvm-branch-commits] [llvm] [AMDGPU][MC] Upstream gfx11/gfx12 true16 assembler test coverage (PR #223826)
Domenic Nutile via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Sep 18 11:51:47 PDT 2026
https://github.com/saxlungs updated https://github.com/llvm/llvm-project/pull/223826
>From 1b55c28579971b6b22ae3a984c93a5689045539b Mon Sep 17 00:00:00 2001
From: Domenic Nutile <domenic.nutile at gmail.com>
Date: Tue, 15 Sep 2026 15:19:15 -0400
Subject: [PATCH] [AMDGPU][MC] Upstream gfx11/gfx12 true16 assembler test
coverage
Upstream new assembler test cases, covering true16 .l/.h operands and op_sel
handling that had no upstream coverage.
---
llvm/test/MC/AMDGPU/gfx11_asm_opsel.s | 69 +++++++++++++++++++
llvm/test/MC/AMDGPU/gfx11_asm_t16.s | 59 ++++++++++++++++
llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s | 5 ++
llvm/test/MC/AMDGPU/gfx12_asm_features.s | 3 +
llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s | 51 ++++++++++++++
llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s | 2 +
6 files changed, 189 insertions(+)
create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_opsel.s
create mode 100644 llvm/test/MC/AMDGPU/gfx11_asm_t16.s
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_opsel.s b/llvm/test/MC/AMDGPU/gfx11_asm_opsel.s
new file mode 100644
index 0000000000000..866b99fdadd8d
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_opsel.s
@@ -0,0 +1,69 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 6
+// RUN: not llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize32,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W32 %s
+// RUN: not llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize64,+real-true16 -show-encoding %s | FileCheck --check-prefixes=GFX11,W64 %s
+// RUN: not llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize32,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize64,+real-true16 -filetype=null %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
+
+// The VGPR suffix is authoritative over the optional op_sel operand
+// We cannot tell the difference between omiting the optional op_sel operand and specifying it to be zero. So conservatively allow this
+v_add_f16 v0.h, v200.l, v2.h op_sel:[0,0,0]
+// GFX11: v_add_f16_e64 v0.h, v200.l, v2.h op_sel:[0,1,1] ; encoding: [0x00,0x50,0x32,0xd5,0xc8,0x05,0x02,0x02]
+
+// op_sel hi on inline imm
+v_med3_f16 v5.h, 2.0, v0.h, v1.h op_sel:[1,1,1,1]
+// GFX11: v_med3_f16 v5.h, 2.0, v0.h, v1.h op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x4f,0xd6,0xf4,0x00,0x06,0x04]
+
+// op_sel hi on literal imm
+v_med3_u16 v5.h, 0xfe0b, v0.h, v1.h op_sel:[1,1,1,1]
+// GFX11: v_med3_u16 v5.h, 0xfe0b, v0.h, v1.h op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x51,0xd6,0xff,0x00,0x06,0x04,0x0b,0xfe,0x00,0x00]
+
+// op_sel hi on sgpr
+v_med3_u16 v5.h, s2, v0.h, v1.h op_sel:[1,1,1,1]
+// GFX11: v_med3_u16 v5.h, s2, v0.h, v1.h op_sel:[1,1,1,1] ; encoding: [0x05,0x78,0x51,0xd6,0x02,0x00,0x06,0x04]
+
+// vopc
+v_cmp_class_f16 s10, s105, v255.h op_sel:[1,1,0]
+// W32: v_cmp_class_f16_e64 s10, s105, v255.h op_sel:[1,1,0] ; encoding: [0x0a,0x18,0x7d,0xd4,0x69,0xfe,0x03,0x02]
+// W64-ERR: :[[@LINE-2]]:17: error: invalid operand for instruction
+
+v_cmp_class_f16 s[10:11], s105, v255.h op_sel:[1,1,0]
+// W32-ERR: :[[@LINE-1]]:17: error: invalid operand for instruction
+// W64: v_cmp_class_f16_e64 s[10:11], s105, v255.h op_sel:[1,1,0] ; encoding: [0x0a,0x18,0x7d,0xd4,0x69,0xfe,0x03,0x02]
+
+// vopcx
+v_cmpx_eq_u16_e64 4, s2 op_sel:[1,1]
+// GFX11: v_cmpx_eq_u16_e64 4, s2 op_sel:[1,1] ; encoding: [0x7e,0x18,0xba,0xd4,0x84,0x04,0x00,0x02]
+
+// vop1
+v_cos_f16_e64 v5.l, -|1.0| op_sel:[1,0]
+// GFX11: v_cos_f16_e64 v5.l, -|1.0| op_sel:[1,0] ; encoding: [0x05,0x09,0xe1,0xd5,0xf2,0x00,0x01,0x22]
+
+// vop2
+v_subrev_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[1,1,1] clamp div:2
+// GFX11: v_subrev_f16_e64 v255.h, -|0xfe0b|, -|vcc_hi| op_sel:[1,1,1] clamp div:2 ; encoding: [0xff,0xdb,0x34,0xd5,0xff,0xd6,0x00,0x7a,0x0b,0xfe,0x00,0x00]
+
+// dpp8
+v_dot2_bf16_bf16_e64_dpp v5.l, v1, -v2, |m0| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0]
+// GFX11: v_dot2_bf16_bf16_e64_dpp v5.l, v1, -v2, |m0| op_sel:[0,0,1,0] dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x24,0x67,0xd6,0xe9,0x04,0xf6,0x41,0x01,0x77,0x39,0x05]
+
+// dpp
+v_minmax_f16_e64_dpp v5.l, v1.l, v2.l, s3 op_sel:[0,0,1,0] row_mirror
+// GFX11: v_minmax_f16_e64_dpp v5.l, v1.l, v2.l, s3 op_sel:[0,0,1,0] row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x20,0x61,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
+
+v_max3_f16 v5.l, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX11: v_max3_f16 v5.l, null, exec_lo, -|0xfe0b| ; encoding: [0x05,0x04,0x4c,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_max3_f16 v255.h, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX11: v_max3_f16 v255.h, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x4c,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_med3_f16 v5.l, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX11: v_med3_f16 v5.l, null, exec_lo, -|0xfe0b| ; encoding: [0x05,0x04,0x4f,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_med3_f16 v255.h, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX11: v_med3_f16 v255.h, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x4f,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
+
+v_min3_f16 v5.l, null, exec_lo, -|0xfe0b| op_sel:[0,0,0,0]
+// GFX11: v_min3_f16 v5.l, null, exec_lo, -|0xfe0b| ; encoding: [0x05,0x04,0x49,0xd6,0x7c,0xfc,0xfc,0x83,0x0b,0xfe,0x00,0x00]
+
+v_min3_f16 v255.h, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp
+// GFX11: v_min3_f16 v255.h, -|0xfe0b|, -|vcc_hi|, null op_sel:[0,0,0,1] clamp ; encoding: [0xff,0xc3,0x49,0xd6,0xff,0xd6,0xf0,0x61,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_t16.s b/llvm/test/MC/AMDGPU/gfx11_asm_t16.s
new file mode 100644
index 0000000000000..2d8a4b4ac3c96
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_t16.s
@@ -0,0 +1,59 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
+// RUN: llvm-mc -triple=amdgpu11.00 -show-encoding -mattr=+real-true16 %s | FileCheck --check-prefix=GFX11 %s
+
+v_add_f16 v0.h, v2.l, v2.h
+// GFX11: v_add_f16_e32 v0.h, v2.l, v2.h ; encoding: [0x02,0x05,0x01,0x65]
+
+v_add_f16 v1.h, s105, v1.l
+// GFX11: v_add_f16_e32 v1.h, s105, v1.l ; encoding: [0x69,0x02,0x02,0x65]
+
+v_add_f16 v1.h, 1.0, v1.l
+// GFX11: v_add_f16_e32 v1.h, 1.0, v1.l ; encoding: [0xf2,0x02,0x02,0x65]
+
+v_add_f16 v1.h, 0x1234, v1.l
+// GFX11: v_add_f16_e32 v1.h, 0x1234, v1.l ; encoding: [0xff,0x02,0x02,0x65,0x34,0x12,0x00,0x00]
+
+v_add_f16 v0.h, v200.l, v2.h
+// GFX11: v_add_f16_e64 v0.h, v200.l, v2.h op_sel:[0,1,1] ; encoding: [0x00,0x50,0x32,0xd5,0xc8,0x05,0x02,0x02]
+
+v_add_f16_e64 v0.l, s2, 0.5
+// GFX11: v_add_f16_e64 v0.l, s2, 0.5 ; encoding: [0x00,0x00,0x32,0xd5,0x02,0xe0,0x01,0x02]
+
+v_add_f16_e64 v0.l, 0.5, s2
+// GFX11: v_add_f16_e64 v0.l, 0.5, s2 ; encoding: [0x00,0x00,0x32,0xd5,0xf0,0x04,0x00,0x02]
+
+v_add_f16 v199.h, 0x1234, v1.l
+// GFX11: v_add_f16_e64 v199.h, 0x1234, v1.l op_sel:[0,0,1] ; encoding: [0xc7,0x40,0x32,0xd5,0xff,0x02,0x02,0x02,0x34,0x12,0x00,0x00]
+
+v_add_f16 v0.h, v1.l, 0x1234
+// GFX11: v_add_f16_e64 v0.h, v1.l, 0x1234 op_sel:[0,0,1] ; encoding: [0x00,0x40,0x32,0xd5,0x01,0xff,0x01,0x02,0x34,0x12,0x00,0x00]
+
+v_mov_b16_e32 v0.l, v1.l
+// GFX11: v_mov_b16_e32 v0.l, v1.l ; encoding: [0x01,0x39,0x00,0x7e]
+
+v_mov_b16_e32 v0.l, s1
+// GFX11: v_mov_b16_e32 v0.l, s1 ; encoding: [0x01,0x38,0x00,0x7e]
+
+v_mov_b16_e32 v0.h, 0
+// GFX11: v_mov_b16_e32 v0.h, 0 ; encoding: [0x80,0x38,0x00,0x7f]
+
+v_mov_b16_e32 v0.h, 1.0
+// GFX11: v_mov_b16_e32 v0.h, 1.0 ; encoding: [0xf2,0x38,0x00,0x7f]
+
+v_mov_b16_e32 v0.l, 0x1234
+// GFX11: v_mov_b16_e32 v0.l, 0x1234 ; encoding: [0xff,0x38,0x00,0x7e,0x34,0x12,0x00,0x00]
+
+v_mov_b16_e64 v0.l, v1.l
+// GFX11: v_mov_b16_e64 v0.l, v1.l ; encoding: [0x00,0x00,0x9c,0xd5,0x01,0x01,0x01,0x02]
+
+v_mov_b16_e64 v200.l, v1.h
+// GFX11: v_mov_b16_e64 v200.l, v1.h op_sel:[1,0] ; encoding: [0xc8,0x08,0x9c,0xd5,0x01,0x01,0x01,0x02]
+
+v_mov_b16_e64 v0.l, s1
+// GFX11: v_mov_b16_e64 v0.l, s1 ; encoding: [0x00,0x00,0x9c,0xd5,0x01,0x00,0x01,0x02]
+
+v_mov_b16_e64 v200.h, 1
+// GFX11: v_mov_b16_e64 v200.h, 1 op_sel:[0,1] ; encoding: [0xc8,0x40,0x9c,0xd5,0x81,0x00,0x01,0x02]
+
+v_mov_b16_e64 v0.l, 0x1234
+// GFX11: v_mov_b16_e64 v0.l, 0x1234 ; encoding: [0x00,0x00,0x9c,0xd5,0xff,0x00,0x01,0x02,0x34,0x12,0x00,0x00]
diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s
index 4a35c9469e196..1b910b968d95c 100644
--- a/llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s
+++ b/llvm/test/MC/AMDGPU/gfx11_asm_vop3_features.s
@@ -75,3 +75,8 @@ v_dot2_bf16_bf16_e64_dpp v0.l, v1, s2, v3.l quad_perm:[0,1,2,3] row_mask:0x0 ban
// Ensure bits 8-15 are not zeroed out and .h which should be present on src0 and dst are present.
v_mul_f16_e64 v5.h, v1.h, v2.l
// GFX11: v_mul_f16_e64 v5.h, v1.h, v2.l op_sel:[1,0,1] ; encoding: [0x05,0x48,0x35,0xd5,0x01,0x05,0x02,0x02]
+
+v_alignbit_b32 v5, v1, v2, 0.5
+// GFX11: v_alignbit_b32 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x16,0xd6,0x01,0x05,0xc2,0x03]
+v_alignbyte_b32 v5, v1, v2, 0.5
+// GFX11: v_alignbyte_b32 v5, v1, v2, 0.5 ; encoding: [0x05,0x00,0x17,0xd6,0x01,0x05,0xc2,0x03]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_features.s b/llvm/test/MC/AMDGPU/gfx12_asm_features.s
index 4edc1e993dcb1..2a8c86e163e12 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_features.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_features.s
@@ -80,3 +80,6 @@ tbuffer_load_d16_format_x v4, off, ttmp[4:7], s3 format:[BUF_FMT_8_UINT] offset:
tbuffer_load_d16_format_x v4, off, ttmp[4:7], s3 format:[BUF_FMT_8_UINT] offset:8388607 scope:SCOPE_SYS th:TH_LOAD_BYPASS
// GFX12: tbuffer_load_d16_format_x v4, off, ttmp[4:7], s3 format:[BUF_FMT_8_UINT] offset:8388607 th:TH_LOAD_BYPASS scope:SCOPE_SYS ; encoding: [0x03,0x00,0x22,0xc4,0x04,0xe0,0xbc,0x02,0x00,0xff,0xff,0x7f]
+
+v_mul_f16_e64 v5.h, v1.h, v2.l
+// GFX12: v_mul_f16_e64 v5.h, v1.h, v2.l op_sel:[1,0,1] ; encoding: [0x05,0x48,0x35,0xd5,0x01,0x05,0x02,0x02]
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
index 3801d09b9f136..66fba21f1d32b 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s
@@ -1026,3 +1026,54 @@ v_trunc_f16_e32 v5.l, v199.l dpp8:[7,6,5,4,3,2,1,0]
v_trunc_f16_e32 v5.l, v199.l quad_perm:[3,2,1,0]
// GFX12: :[[@LINE-1]]:23: error: invalid operand for instruction
+
+v_ceil_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_ceil_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_cos_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_exp_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_exp_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_floor_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_floor_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_floor_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_fract_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_log_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_log_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_log_f16_e32 v255, v1 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+v_log_f16_e32 v255, v1 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+v_log_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_log_f16_e32 v5, v199 dpp8:[7,6,5,4,3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+v_log_f16_e32 v5, v199 quad_perm:[3,2,1,0]
+// GFX12: :[[@LINE-1]]:24: error: invalid operand for instruction
+v_not_b16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:15: error: invalid operand for instruction
+v_rcp_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_rcp_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_rndne_f16_e32 v128, 0xfe0b
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_rsq_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_rsq_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_sat_pk_u8_i16_e32 v199, v5
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_sqrt_f16_e32 v255, v1
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
+v_sqrt_f16_e32 v5, v199
+// GFX12: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
index ebf870223eb9b..f4a31c45d0438 100644
--- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
+++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s
@@ -1,6 +1,8 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
// RUN: not llvm-mc -triple=amdgpu12.00 -mattr=+wavefrontsize32 -filetype=null %s 2>&1 | FileCheck --check-prefix=GFX12 --strict-whitespace --implicit-check-not=error %s
// RUN: not llvm-mc -triple=amdgpu12.00 -mattr=+wavefrontsize64 -filetype=null %s 2>&1 | FileCheck --check-prefix=GFX12 --strict-whitespace --implicit-check-not=error %s
+// RUN: not llvm-mc -triple=amdgpu12.00 -mattr=-real-true16,+wavefrontsize32 -filetype=null %s 2>&1 | FileCheck --check-prefix=GFX12 --strict-whitespace --implicit-check-not=error %s
+// RUN: not llvm-mc -triple=amdgpu12.00 -mattr=-real-true16,+wavefrontsize64 -filetype=null %s 2>&1 | FileCheck --check-prefix=GFX12 --strict-whitespace --implicit-check-not=error %s
v_permlane16_b32 v5, v1, s2, s3 op_sel:[0, 0, 0, 1]
// GFX12: :[[@LINE-1]]:33: error: invalid op_sel operand
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