[llvm-branch-commits] [llvm] [AMDGPU] Legalize sreg32 to vgpr16 conversion when fixing contant bus violation (PR #223898)

[Joe Nash via llvm-branch-commits]

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@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12.00 --stop-after=amdgpu-isel --verify-machineinstrs %s -o - | FileCheck %s
+
+; Make sure the sreg32 and vgpr16 conversion is correct when fixing constant bus violation
+
+define amdgpu_ps half @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %c) {
+
+  ; CHECK-LABEL: name: s_fmaximum3_f16
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr2
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr1
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+  ; CHECK-NEXT:   [[V_MAXIMUM3_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MAXIMUM3_F16_t16_e64 0, [[COPY2]], 0, [[COPY1]], 0, [[COPY3]].lo16, 0, 0, 0, implicit $exec
+  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+  ; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[V_MAXIMUM3_F16_t16_e64_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:sgpr_32 = COPY killed [[REG_SEQUENCE]]
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Sisyph wrote:

Why do we COPY REG_SEQUENCE to sgpr and then back to vgpr?

https://github.com/llvm/llvm-project/pull/223898