[llvm-branch-commits] [llvm] [AMDGPU] Classify generic-target features (PR #223179)
Chinmay Deshpande via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Sep 17 10:50:38 PDT 2026
https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/223179
>From 5b022266575cdf397446747102797f879f04f300 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Mon, 14 Sep 2026 10:51:34 -0700
Subject: [PATCH] [AMDGPU] Classify generic-target features
Classify features used by generic targets but absent from some covered
GPUs as AMDGPUGenericAnyFeature. This covers the gfx11 workarounds,
gfx12.5 register fixup and WMMA timing, and LDS size and bank count.
Derive the classified features directly from the SubtargetFeature subclass
and preserve their existing predicates. Keep RequiresCOV6 outside this
policy because it is specific to generic targets and absent from their
covered GPUs.
Test the real target definitions, missing support for classified features,
and the existing all-member requirement for instruction capabilities.
Change-Id: I9fffbe532b8b5bc8875f20f394f29e2e6899f52e
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 64 ++++++++++-------
llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 6 +-
.../AMDGPUTargetDefGenericClassification.td | 70 +++++++++++++++++++
.../TableGen/Basic/AMDGPUTargetDefEmitter.cpp | 2 -
4 files changed, 113 insertions(+), 29 deletions(-)
create mode 100644 llvm/test/TableGen/AMDGPUTargetDefGenericClassification.td
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index b0fa161645ad44..75c5b08eaf6f50 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -260,9 +260,10 @@ defm SGPRInitBug : AMDGPUSubtargetFeature<"sgpr-init-bug",
/*GenPredicate=*/1, /*GenAssemblerPredicate=*/1, [], InlineIgnore
>;
-defm UserSGPRInit16Bug : AMDGPUSubtargetFeature<"user-sgpr-init16-bug",
- "Bug requiring at least 16 user+system SGPRs to be enabled",
- /*GenPredicate=*/0
+def FeatureUserSGPRInit16Bug : AMDGPUGenericAnyFeature<"user-sgpr-init16-bug",
+ "HasUserSGPRInit16Bug",
+ "true",
+ "Bug requiring at least 16 user+system SGPRs to be enabled"
>;
defm LDSMisalignedBug : AMDGPUSubtargetFeature<"lds-misaligned-bug",
@@ -386,23 +387,28 @@ defm ImageGather4D16Bug : AMDGPUSubtargetFeature<"image-gather4-d16-bug",
/*GenPredicate=*/0
>;
-defm MADIntraFwdBug : AMDGPUSubtargetFeature<"mad-intra-fwd-bug",
- "MAD_U64/I64 intra instruction forwarding bug",
- /*GenPredicate=*/1,
- /*GenAssemblerPredicate=*/0
+def FeatureMADIntraFwdBug : AMDGPUGenericAnyFeature<"mad-intra-fwd-bug",
+ "HasMADIntraFwdBug",
+ "true",
+ "MAD_U64/I64 intra instruction forwarding bug"
>;
-defm MSAALoadDstSelBug : AMDGPUSubtargetFeature<"msaa-load-dst-sel-bug",
- "MSAA loads not honoring dst_sel bug",
- /*GenPredicate=*/0
+def HasMADIntraFwdBug : Predicate<"Subtarget->hasMADIntraFwdBug()">;
+
+def FeatureMSAALoadDstSelBug : AMDGPUGenericAnyFeature<"msaa-load-dst-sel-bug",
+ "HasMSAALoadDstSelBug",
+ "true",
+ "MSAA loads not honoring dst_sel bug"
>;
-defm PrivEnabledTrap2NopBug : AMDGPUSubtargetFeature<"priv-enabled-trap2-nop-bug",
- "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug",
- /*GenPredicate=*/0
+def FeaturePrivEnabledTrap2NopBug : AMDGPUGenericAnyFeature<"priv-enabled-trap2-nop-bug",
+ "HasPrivEnabledTrap2NopBug",
+ "true",
+ "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug"
>;
-class SubtargetFeatureLDSBankCount <int Value> : SubtargetFeature <
+// A generic target may use an LDS bank count from one of its covered GPUs.
+class SubtargetFeatureLDSBankCount <int Value> : AMDGPUGenericAnyFeature <
"ldsbankcount"#Value,
"LDSBankCount",
!cast<string>(Value),
@@ -1126,10 +1132,15 @@ defm GFX1251GEMMInsts : AMDGPUSubtargetFeature<"gfx1251-gemm-insts",
"Has additional gfx1251 DGEMM instructions"
>;
-defm GFX125xLowestRateWMMA : AMDGPUSubtargetFeature<"gfx125x-lowest-rate-wmma",
+def FeatureGFX125xLowestRateWMMA : AMDGPUGenericAnyFeature<"gfx125x-lowest-rate-wmma",
+ "HasGFX125xLowestRateWMMA",
+ "true",
"Has the lowest rate wmma in the gfx125x family, mainly for the gfx12-5-generic"
>;
+def HasGFX125xLowestRateWMMA : Predicate<"Subtarget->hasGFX125xLowestRateWMMA()">,
+ AssemblerPredicate<(any_of FeatureGFX125xLowestRateWMMA)>;
+
defm FlatBufferGlobalAtomicFaddF64Inst : AMDGPUSubtargetFeature<"flat-buffer-global-fadd-f64-inst",
"Has flat, buffer, and global instructions for f64 atomic fadd"
>;
@@ -1240,9 +1251,10 @@ defm VOPDInsts : AMDGPUSubtargetFeature<"vopd",
/*GenPredicate=*/0
>;
-defm VALUTransUseHazard : AMDGPUSubtargetFeature<"valu-trans-use-hazard",
- "Hazard when TRANS instructions are closely followed by a use of the result",
- /*GenPredicate=*/0
+def FeatureVALUTransUseHazard : AMDGPUGenericAnyFeature<"valu-trans-use-hazard",
+ "HasVALUTransUseHazard",
+ "true",
+ "Hazard when TRANS instructions are closely followed by a use of the result"
>;
defm TransCoexecutionHazard : AMDGPUSubtargetFeature<"trans-coexecution-hazard",
@@ -1271,9 +1283,10 @@ defm RestrictedSOffset : AMDGPUSubtargetFeature<"restricted-soffset",
"Has restricted SOffset (immediate not supported)."
>;
-defm RequiredExportPriority : AMDGPUSubtargetFeature<"required-export-priority",
- "Export priority must be explicitly manipulated on GFX11.5",
- /*GenPredicate=*/0
+def FeatureRequiredExportPriority : AMDGPUGenericAnyFeature<"required-export-priority",
+ "HasRequiredExportPriority",
+ "true",
+ "Export priority must be explicitly manipulated on GFX11.5"
>;
defm VmemWriteVgprInOrder : AMDGPUSubtargetFeature<"vmem-write-vgpr-in-order",
@@ -1318,9 +1331,10 @@ defm 1024AddressableVGPRs : AMDGPUSubtargetFeature<"1024-addressable-vgprs",
"Has 1024 addressable VGPRs"
>;
-defm SetregVGPRMSBFixup : AMDGPUSubtargetFeature<"setreg-vgpr-msb-fixup",
- "S_SETREG to MODE clobbers VGPR MSB bits, requires fixup",
- /*GenPredicate=*/0
+def FeatureSetregVGPRMSBFixup : AMDGPUGenericAnyFeature<"setreg-vgpr-msb-fixup",
+ "HasSetregVGPRMSBFixup",
+ "true",
+ "S_SETREG to MODE clobbers VGPR MSB bits, requires fixup"
>;
defm WaitXcnt : AMDGPUSubtargetFeature<"wait-xcnt",
@@ -1493,6 +1507,8 @@ defm GWS : AMDGPUSubtargetFeature<"gws",
/*GenAssemblerPredicate=*/0
>;
+// Generic targets require code object v6 independently of their covered GPUs,
+// so this feature does not use the any-covered-GPU classification.
def FeatureRequiresCOV6 : SubtargetFeature<"requires-cov6",
"RequiresCOV6",
"true",
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
index 1d398830f07c67..3e1655529ffbf3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td
@@ -31,8 +31,9 @@ def FeatureFlatOffsetBits12 : SubtargetFeatureFlatOffsetBits<12>;
def FeatureFlatOffsetBits24 : SubtargetFeatureFlatOffsetBits<24>;
// Addressable local memory size is the maximum number of bytes of LDS that can
-// be allocated to a single workgroup.
-class SubtargetFeatureAddressableLocalMemorySize <int Value> : SubtargetFeature<
+// be allocated to a single workgroup. A generic target's feature must be present
+// on at least one of its covered GPUs.
+class SubtargetFeatureAddressableLocalMemorySize <int Value> : AMDGPUGenericAnyFeature<
"addressablelocalmemorysize"#Value,
"AddressableLocalMemorySize",
!cast<string>(Value),
@@ -77,4 +78,3 @@ class SubtargetFeatureGeneration <string Value, string FeatureName,
list<SubtargetFeature> Implies> :
SubtargetFeature <FeatureName, "Gen", Subtarget#"::"#Value,
Value#" GPU generation", Implies>;
-
diff --git a/llvm/test/TableGen/AMDGPUTargetDefGenericClassification.td b/llvm/test/TableGen/AMDGPUTargetDefGenericClassification.td
new file mode 100644
index 00000000000000..a23c4a61059b44
--- /dev/null
+++ b/llvm/test/TableGen/AMDGPUTargetDefGenericClassification.td
@@ -0,0 +1,70 @@
+// RUN: split-file %s %t
+// RUN: llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/valid.td \
+// RUN: | FileCheck %t/valid.td
+// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/missing-bug.td 2>&1 \
+// RUN: | FileCheck %t/missing-generic.td -DFILE=%t/missing-generic.td -DFEATURE=user-sgpr-init16-bug --implicit-check-not="error:"
+// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/missing-priority.td 2>&1 \
+// RUN: | FileCheck %t/missing-generic.td -DFILE=%t/missing-generic.td -DFEATURE=required-export-priority --implicit-check-not="error:"
+// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/missing-timing.td 2>&1 \
+// RUN: | FileCheck %t/missing-generic.td -DFILE=%t/missing-generic.td -DFEATURE=gfx125x-lowest-rate-wmma --implicit-check-not="error:"
+// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/missing-banks.td 2>&1 \
+// RUN: | FileCheck %t/missing-generic.td -DFILE=%t/missing-generic.td -DFEATURE=ldsbankcount32 --implicit-check-not="error:"
+// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/missing-lds-size.td 2>&1 \
+// RUN: | FileCheck %t/missing-generic.td -DFILE=%t/missing-generic.td -DFEATURE=addressablelocalmemorysize65536 --implicit-check-not="error:"
+// RUN: not llvm-tblgen -gen-amdgpu-target-def -I %t -I %p/../../include -I %p/../../lib/Target/AMDGPU %t/capability.td 2>&1 \
+// RUN: | FileCheck %t/capability.td -DFILE=%t/capability.td --implicit-check-not="error:"
+
+//--- common.td
+include "AMDGPU.td"
+
+def EmptyGPU : AMDGPUProcessorModel<"gfx999", NoSchedModel, [], [9, 9, 9]>;
+
+//--- valid.td
+include "common.td"
+// Check the real generic targets, including gfx11's combined workarounds,
+// gfx12-5's fixup and WMMA timing, and gfx9-4's LDS size and bank count.
+// CHECK: GK_GFX9_4_GENERIC
+// CHECK: GK_GFX11_GENERIC
+// CHECK: GK_GFX12_5_GENERIC
+
+//--- missing-bug.td
+include "common.td"
+defvar CheckedFeature = FeatureUserSGPRInit16Bug;
+include "missing-generic.td"
+
+//--- missing-priority.td
+include "common.td"
+defvar CheckedFeature = FeatureRequiredExportPriority;
+include "missing-generic.td"
+
+//--- missing-timing.td
+include "common.td"
+defvar CheckedFeature = FeatureGFX125xLowestRateWMMA;
+include "missing-generic.td"
+
+//--- missing-banks.td
+include "common.td"
+defvar CheckedFeature = FeatureLDSBankCount32;
+include "missing-generic.td"
+
+//--- missing-lds-size.td
+include "common.td"
+defvar CheckedFeature = FeatureAddressableLocalMemorySize65536;
+include "missing-generic.td"
+
+//--- missing-generic.td
+// Classified backend-only features still need support from a covered GPU.
+// CHECK: [[FILE]]:[[#@LINE+1]]:1: error: generic target 'gfx9-9-generic' exposes feature '[[FEATURE]]' not supported by any covered GPU
+def : AMDGPUProcessorModel<"gfx9-9-generic", NoSchedModel, [CheckedFeature], [9, 9, 0]> {
+ let CoveredGPUs = [EmptyGPU];
+}
+
+//--- capability.td
+include "common.td"
+def WMMAGPU : AMDGPUProcessorModel<"gfx998", NoSchedModel,
+ [FeatureWMMA256bInsts], [9, 9, 8]>;
+// Instruction support keeps the default all-covered-GPUs rule.
+// CHECK: [[FILE]]:[[#@LINE+1]]:1: error: generic target 'gfx9-9-generic' exposes feature 'wmma-256b-insts' not supported by covered GPU 'gfx999'
+def : AMDGPUProcessorModel<"gfx9-9-generic", NoSchedModel, [FeatureWMMA256bInsts], [9, 9, 0]> {
+ let CoveredGPUs = [WMMAGPU, EmptyGPU];
+}
diff --git a/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp b/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
index ba578313333343..5132c2d1d520ac 100644
--- a/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
+++ b/llvm/utils/TableGen/Basic/AMDGPUTargetDefEmitter.cpp
@@ -479,8 +479,6 @@ collectGenericFeatures(const Record *GPU,
// Ordinary frontend-visible features must be present on every covered GPU.
// AMDGPUGenericAnyFeature features need only be present on one covered GPU.
-//
-// FIXME: Classify the remaining backend-only features before checking them.
static void
validateGenericFeatures(const Record *GPU,
const DenseMap<const Record *, unsigned> &FeatureIdx) {
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