[llvm-branch-commits] [llvm] [AMDGPU] Insert MFMA anti-hints in GCNPreRAOptimizations (PR #218075)

[Quentin Colombet via llvm-branch-commits]

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@@ -0,0 +1,510 @@
+//===-- GCNPreRAAntiHints.cpp - MFMA register anti-hints ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// Insert register allocation anti-hints.
+///
+//===----------------------------------------------------------------------===//
+
+#include "GCNPreRAAntiHints.h"
+#include "GCNSubtarget.h"
+#include "SIInstrInfo.h"
+#include "SIRegisterInfo.h"
+#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetSchedule.h"
+
+using namespace llvm;
+using namespace llvm::AMDGPU;
+
+#define DEBUG_TYPE "amdgpu-anti-hints"
+
+namespace HC = llvm::AMDGPU::HazardClass;
+
+static cl::opt<std::string> AntiHintRuleSelection(
+    "amdgpu-anti-hints-rules", cl::Hidden,
+    cl::desc("Comma-separated anti-hints rules (waw, war), or all or none."),
+    cl::init("all"));
+
+namespace {
+
+// Classify the MI into a HazardClassMask.
+HazardClassMask getInstHazardClass(const MachineInstr &MI,
+                                   const HazardContext &Ctx) {
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qcolombet wrote:

I'm assuming we need similar logic in the passes that deal with hazard protection like the HazardRecognizer and InsertWait passes.
We'll need a way to share this information across all these passes.

@kerbowa, @vporpo do you know where the relevant pieces currently live?

https://github.com/llvm/llvm-project/pull/218075