[llvm-branch-commits] [clang] [clang][AArch64] Consolidate codegen tests for SVE's DUP intrinsics (PR #223933)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Sep 16 00:25:43 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-clang
Author: Andrzej Warzyński (banach-space)
<details>
<summary>Changes</summary>
This patch completes the migration of the tests from:
* clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c
to:
* clang/test/CodeGen/AArch64/sve/dup.c
`dup.c` covers all the cases previously tested by `acle_sve_dup.c`.
However, unlike `acle_sve_dup.c`, it was only tested as C. Add `-x c++`
RUN lines to provide the equivalent C++ coverage, including lowering
via CIR.
---
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---
Patch is 101.59 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223933.diff
2 Files Affected:
- (removed) clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c (-1130)
- (modified) clang/test/CodeGen/AArch64/sve/dup.c (+146-80)
``````````diff
diff --git a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c b/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c
deleted file mode 100644
index e76a5df69fc5f9..00000000000000
--- a/clang/test/CodeGen/AArch64/sve-intrinsics/acle_sve_dup.c
+++ /dev/null
@@ -1,1130 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
-// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -o /dev/null %s
-
-#include <arm_sve.h>
-
-#if defined __ARM_FEATURE_SME
-#define MODE_ATTR __arm_streaming
-#else
-#define MODE_ATTR
-#endif
-
-#ifdef SVE_OVERLOADED_FORMS
-// A simple used,unused... macro, long enough to represent any SVE builtin.
-#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
-#else
-#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
-#endif
-
-// CHECK-LABEL: @test_svdup_n_s8(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svdup_n_s8a(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-svint8_t test_svdup_n_s8(int8_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s8,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_s16s(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-svint16_t test_svdup_n_s16(int16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s16,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_s32i(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-svint32_t test_svdup_n_s32(int32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s32,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s64(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_s64l(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-svint64_t test_svdup_n_s64(int64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s64,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u8(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z15test_svdup_n_u8h(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 16 x i8> [[DOTSPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-svuint8_t test_svdup_n_u8(uint8_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u8,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_u16t(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x i16> poison, i16 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 8 x i16> [[DOTSPLATINSERT]], <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP0]]
-//
-svuint16_t test_svdup_n_u16(uint16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u16,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_u32j(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 4 x i32> [[DOTSPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP0]]
-//
-svuint32_t test_svdup_n_u32(uint32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u32,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u64(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_u64m(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 2 x i64> [[DOTSPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP0]]
-//
-svuint64_t test_svdup_n_u64(uint64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u64,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_f16(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x half> poison, half [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 8 x half> [[DOTSPLATINSERT]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_f16Dh(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 8 x half> poison, half [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 8 x half> [[DOTSPLATINSERT]], <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
-//
-svfloat16_t test_svdup_n_f16(float16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_f16,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_f32(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x float> poison, float [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 4 x float> [[DOTSPLATINSERT]], <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_f32f(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 4 x float> poison, float [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 4 x float> [[DOTSPLATINSERT]], <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
-//
-svfloat32_t test_svdup_n_f32(float32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_f32,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_f64(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x double> poison, double [[OP:%.*]], i64 0
-// CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 2 x double> [[DOTSPLATINSERT]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
-// CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z16test_svdup_n_f64d(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <vscale x 2 x double> poison, double [[OP:%.*]], i64 0
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = shufflevector <vscale x 2 x double> [[DOTSPLATINSERT]], <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
-// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP0]]
-//
-svfloat64_t test_svdup_n_f64(float64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_f64,)(op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s8_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], i8 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z17test_svdup_n_s8_zu10__SVBool_ta(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], i8 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-svint8_t test_svdup_n_s8_z(svbool_t pg, int8_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s8_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s16_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], i16 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_s16_zu10__SVBool_ts(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], i16 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
-//
-svint16_t test_svdup_n_s16_z(svbool_t pg, int16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s16_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s32_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], i32 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_s32_zu10__SVBool_ti(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], i32 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
-//
-svint32_t test_svdup_n_s32_z(svbool_t pg, int32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s32_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_s64_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], i64 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_s64_zu10__SVBool_tl(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], i64 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
-//
-svint64_t test_svdup_n_s64_z(svbool_t pg, int64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_s64_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u8_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], i8 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-// CPP-CHECK-LABEL: @_Z17test_svdup_n_u8_zu10__SVBool_th(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], i8 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
-//
-svuint8_t test_svdup_n_u8_z(svbool_t pg, uint8_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u8_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u16_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], i16 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_u16_zu10__SVBool_tt(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.dup.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], i16 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
-//
-svuint16_t test_svdup_n_u16_z(svbool_t pg, uint16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u16_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u32_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], i32 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_u32_zu10__SVBool_tj(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], i32 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
-//
-svuint32_t test_svdup_n_u32_z(svbool_t pg, uint32_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u32_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_u64_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], i64 [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_u64_zu10__SVBool_tm(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.dup.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], i64 [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
-//
-svuint64_t test_svdup_n_u64_z(svbool_t pg, uint64_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_u64_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_f16_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.dup.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> [[TMP0]], half [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
-//
-// CPP-CHECK-LABEL: @_Z18test_svdup_n_f16_zu10__SVBool_tDh(
-// CPP-CHECK-NEXT: entry:
-// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[PG:%.*]])
-// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.dup.nxv8f16(<vscale x 8 x half> zeroinitializer, <vscale x 8 x i1> [[TMP0]], half [[OP:%.*]])
-// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
-//
-svfloat16_t test_svdup_n_f16_z(svbool_t pg, float16_t op) MODE_ATTR
-{
- return SVE_ACLE_FUNC(svdup,_n,_f16_z,)(pg, op);
-}
-
-// CHECK-LABEL: @test_svdup_n_f32_z(
-// CHECK-NEXT: entry:
-// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
-// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.dup.nxv4f32(<vscale x 4 x float> zeroinitializer, <vscale x 4 x i1> [[TMP0]], float [[OP:%.*]])
-// CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
-//
-// C...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223933
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