[llvm-branch-commits] [llvm] [AMDGPU] Legalize sreg32 to vgpr16 conversion when fixing contant bus violation (PR #223898)
Guo Chen via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 15 19:07:40 PDT 2026
https://github.com/broxigarchen created https://github.com/llvm/llvm-project/pull/223898
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>From a1166edfa6310a019fa73861fcdc54118e614ad8 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 15 Sep 2026 21:18:07 -0400
Subject: [PATCH 1/2] legalizeOpWithMove check for sgpr32 to vgpr16 case
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 11 ++-
llvm/test/CodeGen/AMDGPU/bf16.ll | 68 ++++++++---------
.../CodeGen/AMDGPU/extract-hi16-true16.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fmaximum3.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fminimum3.ll | 4 +-
.../CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll | 3 +-
.../test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll | 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/minmax.ll | 12 +--
llvm/test/CodeGen/AMDGPU/select.f16.ll | 75 +++++++++----------
10 files changed, 91 insertions(+), 94 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index dac7f39842c6d5..1d2e10847e7101 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6512,7 +6512,16 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
BuildMI(*MBB, I, DL, get(Opcode), Reg)
.addImm(0) // src0_modifiers
.add(MO)
- .addImm(0); // op_sel
+ .addImm(0); // op_sel
+ } else if (Size == 16 && ST.useRealTrue16Insts() && Opcode == AMDGPU::COPY) {
+ // SGPR32 to VGPR16
+ const TargetRegisterClass *CurrRC = MRI.getRegClass(MO.getReg());
+ const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(CurrRC);
+ Register Reg = MRI.createVirtualRegister(VRC);
+ BuildMI(*MBB, I, DL, get(Opcode), Reg).add(MO);
+ MO.ChangeToRegister(Reg, false);
+ legalizeOperandsVALUt16(MI, OpIdx, MRI);
+ return;
} else {
BuildMI(*MBB, I, DL, get(Opcode), Reg).add(MO);
}
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index 62008732a9a7a0..f5c6ce454f8305 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -41194,7 +41194,7 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) #0
; GFX11TRUE16-LABEL: s_select_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, vcc_lo
; GFX11TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
@@ -41220,7 +41220,7 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) #0
; GFX1250TRUE16-NEXT: v_nop
; GFX1250TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX1250TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, vcc_lo
; GFX1250TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
@@ -41433,14 +41433,13 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX11TRUE16-NEXT: s_lshr_b32 s3, s0, 16
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s1, 16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v0.l, s2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.l, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, s1, v0.h, vcc_lo
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v1.l, vcc_lo
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_vselect_v2bf16:
@@ -41468,14 +41467,13 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX1250TRUE16-NEXT: s_lshr_b32 s3, s0, 16
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250TRUE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s1, 16
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v0.l, s2
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.l, s2
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, s1, v0.h, vcc_lo
-; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v1.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250FAKE16-LABEL: s_vselect_v2bf16:
@@ -42580,19 +42578,18 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v1
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v2
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s1
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s7 :: v_dual_mov_b32 v1, s9
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11TRUE16-NEXT: s_lshr_b32 s8, s3, 16
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s2, 16
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, s8, v0.l, s6
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.h, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s2, v1.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, s3, v1.h, s5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, s8, v0.l, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v1.l, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, s2, v2.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s3, v3.l, s5
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_vselect_v4bf16:
@@ -42635,19 +42632,18 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v1
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v2
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v3
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, s9
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, s1
+; GFX1250TRUE16-NEXT: v_dual_mov_b32 v0, s7 :: v_dual_mov_b32 v1, s9
+; GFX1250TRUE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250TRUE16-NEXT: s_lshr_b32 s8, s3, 16
; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s2, 16
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, s8, v0.l, s6
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.h, s4
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s2, v1.l, vcc_lo
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, s3, v1.h, s5
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s8, v0.l, s6
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v1.l, s4
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, s2, v2.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s3, v3.l, s5
+; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s1, v0
; GFX1250TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250FAKE16-LABEL: s_vselect_v4bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll b/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
index 0a8ac4b00f3a32..ca5be2f84b4fe1 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-hi16-true16.ll
@@ -191,11 +191,11 @@ define amdgpu_cs void @no_extract_hi16_uniform_sgpr(<2 x half> inreg %v, ptr add
; GFX12-TRUE16-NEXT: s_mov_b32 s3, s2
; GFX12-TRUE16-NEXT: s_mov_b32 s2, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, 0
; GFX12-TRUE16-NEXT: s_cmp_eq_f16 s0, s1
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_cselect_b32 s0, -1, 0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, s0
; GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[2:3]
; GFX12-TRUE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
index db4d0fa13c62b0..5e7bd87ecfafb1 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
@@ -1557,7 +1557,7 @@ define half @v_fmaximum3_f16_commute(half %a, half %b, half %c) {
define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %c) {
; GFX12-TRUE16-LABEL: s_fmaximum3_f16:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_maximum3_f16 v0.l, s0, s1, v0.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1579,7 +1579,7 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
;
; GFX1170-TRUE16-LABEL: s_fmaximum3_f16:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_maximum3_f16 v0.l, s0, s1, v0.l
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
index 8c4d6f42ff8502..b2d788280db87a 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
@@ -1557,7 +1557,7 @@ define half @v_fminimum3_f16_commute(half %a, half %b, half %c) {
define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %c) {
; GFX12-TRUE16-LABEL: s_fminimum3_f16:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_minimum3_f16 v0.l, s0, s1, v0.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1579,7 +1579,7 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
;
; GFX1170-TRUE16-LABEL: s_fminimum3_f16:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_minimum3_f16 v0.l, s0, s1, v0.l
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
index de05fe56b8428b..361a1e88e5271b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
@@ -92,9 +92,8 @@ define amdgpu_kernel void @v_alignbyte_b32(ptr addrspace(1) %out, i32 %src1, i32
; GFX11-TRUE16-SDAG-NEXT: s_clause 0x1
; GFX11-TRUE16-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-TRUE16-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-SDAG-NEXT: v_alignbyte_b32 v0, s0, s1, v0.l
; GFX11-TRUE16-SDAG-NEXT: global_store_b32 v1, v0, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
index 3b5000fc4443d5..cd41c21ac88623 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
@@ -303,7 +303,7 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
; GFX1250-SDG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-SDG-TRUE16-NEXT: v_nop
; GFX1250-SDG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-SDG-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
index e284f99fa05b6e..aba6798a0471a7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
@@ -150,7 +150,7 @@ entry:
define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry
-; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1
+; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1
; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_dot2_bf16_bf16 v2.l, s0, 0x3f803f80, v2.l
; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index c3bf35ae4ed53f..f208ed699712c1 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -1040,8 +1040,7 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b, half inreg %c, ptr addrspace(1) inreg %out) {
; SDAG-GFX11-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX11-TRUE16: ; %bb.0:
-; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX11-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX11-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, s0, s1, v0.l
@@ -1078,8 +1077,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX1170-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX1170-TRUE16: ; %bb.0:
-; SDAG-GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX1170-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX1170-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1170-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1170-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
@@ -1119,8 +1117,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX12-TRUE16: ; %bb.0:
-; SDAG-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
@@ -1164,8 +1161,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
; SDAG-GFX1250-TRUE16-NEXT: v_nop
; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; SDAG-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX1250-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
diff --git a/llvm/test/CodeGen/AMDGPU/select.f16.ll b/llvm/test/CodeGen/AMDGPU/select.f16.ll
index 5472a161fd876c..1ea0502aa8837b 100644
--- a/llvm/test/CodeGen/AMDGPU/select.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select.f16.ll
@@ -830,37 +830,36 @@ define amdgpu_kernel void @select_v2f16(
; GFX11-TRUE16-NEXT: s_mov_b32 s23, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s18, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s19, s3
-; GFX11-TRUE16-NEXT: s_mov_b32 s26, s2
-; GFX11-TRUE16-NEXT: s_mov_b32 s27, s3
; GFX11-TRUE16-NEXT: s_mov_b32 s6, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s7, s3
+; GFX11-TRUE16-NEXT: s_mov_b32 s26, s2
+; GFX11-TRUE16-NEXT: s_mov_b32 s27, s3
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s20, s12
; GFX11-TRUE16-NEXT: s_mov_b32 s21, s13
; GFX11-TRUE16-NEXT: s_mov_b32 s16, s10
; GFX11-TRUE16-NEXT: s_mov_b32 s17, s11
+; GFX11-TRUE16-NEXT: buffer_load_b32 v0, off, s[20:23], 0
+; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[16:19], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s24, s14
; GFX11-TRUE16-NEXT: s_mov_b32 s25, s15
-; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[20:23], 0
-; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[16:19], 0
+; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[4:7], 0
; GFX11-TRUE16-NEXT: buffer_load_b32 v3, off, s[24:27], 0
-; GFX11-TRUE16-NEXT: buffer_load_b32 v4, off, s[4:7], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, s9
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s0, v1.l, v0.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v4
-; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s0, v2.l, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v5.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, v5.l, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v3.l, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -1014,26 +1013,25 @@ define amdgpu_kernel void @select_v2f16_imm_a(
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s7
; GFX11-TRUE16-NEXT: s_mov_b32 s16, s8
+; GFX11-TRUE16-NEXT: buffer_load_b32 v0, off, s[12:15], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s17, s9
-; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[12:15], 0
-; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[16:19], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s20, s10
; GFX11-TRUE16-NEXT: s_mov_b32 s21, s11
+; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[16:19], 0
+; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[20:23], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, s5
-; GFX11-TRUE16-NEXT: buffer_load_b32 v3, off, s[20:23], 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s0, 0.5, v0.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e64 s0, 0.5, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, 0x3900, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_lt_f16_e32 vcc_lo, 0x3900, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -1180,26 +1178,25 @@ define amdgpu_kernel void @select_v2f16_imm_b(
; GFX11-TRUE16-NEXT: s_mov_b32 s12, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s13, s7
; GFX11-TRUE16-NEXT: s_mov_b32 s16, s8
+; GFX11-TRUE16-NEXT: buffer_load_b32 v0, off, s[12:15], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s17, s9
-; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[12:15], 0
-; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[16:19], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s20, s10
; GFX11-TRUE16-NEXT: s_mov_b32 s21, s11
+; GFX11-TRUE16-NEXT: buffer_load_b32 v1, off, s[16:19], 0
+; GFX11-TRUE16-NEXT: buffer_load_b32 v2, off, s[20:23], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s1, s5
-; GFX11-TRUE16-NEXT: buffer_load_b32 v3, off, s[20:23], 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e64 s0, 0.5, v0.l
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e64 s0, 0.5, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0x3900, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v0.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0x3900, v3.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_mov_b32 s0, s4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
>From e10b4a1abead4724dce8668b7b7078f56e561b20 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 15 Sep 2026 22:05:28 -0400
Subject: [PATCH 2/2] added mir test
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 +-
.../constant-bus-illegal-fold-true16.ll | 54 +++++++++++++++++++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/constant-bus-illegal-fold-true16.ll
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 1d2e10847e7101..bf94f127933ce7 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6512,7 +6512,7 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
BuildMI(*MBB, I, DL, get(Opcode), Reg)
.addImm(0) // src0_modifiers
.add(MO)
- .addImm(0); // op_sel
+ .addImm(0); // op_sel
} else if (Size == 16 && ST.useRealTrue16Insts() && Opcode == AMDGPU::COPY) {
// SGPR32 to VGPR16
const TargetRegisterClass *CurrRC = MRI.getRegClass(MO.getReg());
diff --git a/llvm/test/CodeGen/AMDGPU/constant-bus-illegal-fold-true16.ll b/llvm/test/CodeGen/AMDGPU/constant-bus-illegal-fold-true16.ll
new file mode 100644
index 00000000000000..b0bff5cd284fd0
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/constant-bus-illegal-fold-true16.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu12.00 --stop-after=amdgpu-isel --verify-machineinstrs %s -o - | FileCheck %s
+
+; Make sure the sreg32 and vgpr16 conversion is correct when fixing constant bus violation
+
+define amdgpu_ps half @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %c) {
+
+ ; CHECK-LABEL: name: s_fmaximum3_f16
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+ ; CHECK-NEXT: [[V_MAXIMUM3_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MAXIMUM3_F16_t16_e64 0, [[COPY2]], 0, [[COPY1]], 0, [[COPY3]].lo16, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[V_MAXIMUM3_F16_t16_e64_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY killed [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY4]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_16 = COPY [[COPY5]].lo16
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY6]]
+ ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0
+ %max0 = call half @llvm.maximum.f16(half %a, half %b)
+ %max1 = call half @llvm.maximum.f16(half %max0, half %c)
+ ret half %max1
+}
+
+
+define amdgpu_ps half @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %c) {
+
+ ; CHECK-LABEL: name: s_fminimum3_f16
+ ; CHECK: bb.0 (%ir-block.0):
+ ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_32 = COPY $sgpr2
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+ ; CHECK-NEXT: [[V_MINIMUM3_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MINIMUM3_F16_t16_e64 0, [[COPY2]], 0, [[COPY1]], 0, [[COPY3]].lo16, 0, 0, 0, implicit $exec
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[V_MINIMUM3_F16_t16_e64_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY killed [[REG_SEQUENCE]]
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY killed [[COPY4]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_16 = COPY [[COPY5]].lo16
+ ; CHECK-NEXT: $vgpr0 = COPY [[COPY6]]
+ ; CHECK-NEXT: SI_RETURN_TO_EPILOG $vgpr0
+ %max0 = call half @llvm.minimum.f16(half %a, half %b)
+ %max1 = call half @llvm.minimum.f16(half %max0, half %c)
+ ret half %max1
+}
+
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