[llvm-branch-commits] [llvm] [AMDGPU][MC] Upstream gfx12 true16 disassembler test coverage (PR #223825)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 15 13:56:07 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Domenic Nutile (saxlungs)
<details>
<summary>Changes</summary>
Upstream new gfx12 disassembler test cases, covering true16 operand (.l/.h)
and op_sel decoding for f16 opcodes that had no upstream coverage:
---
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---
Patch is 73.88 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/223825.diff
11 Files Affected:
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt (+5)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt (+7)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt (+51)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt (+31)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt (+26)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt (+64)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt (+64)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt (+64)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2.txt (+41)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp16.txt (+134)
- (modified) llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop2_dpp8.txt (+69)
``````````diff
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
index bc0519b18e5ecd..f0d3c209779f44 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
@@ -16,6 +16,11 @@
0x05,0x00,0x55,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff
# GFX12: v_add3_u32_e64_dpp v5, v1, s2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff]
+0x05,0x00,0x03,0xd5,0xfa,0x04,0x00,0x00,0x01,0x40,0x01,0xff
+# GFX12: v_add_f32_e64_dpp v5, v1, s2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x03,0xd5,0xfa,0x04,0x00,0x00,0x01,0x40,0x01,0xff]
+0x05,0x48,0x35,0xd5,0x01,0x05,0x02,0x00
+# GFX12: v_mul_f16_e64 v5.h, v1.h, v2.l op_sel:[1,0,1] ; encoding: [0x05,0x48,0x35,0xd5,0x01,0x05,0x02,0x02]
+
# Regression test for future fixes to VOPC _e64_dpp src1
0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff
# GFX12: v_cmp_le_f32 vcc_lo, v1, v2 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x04,0x26,0x7c,0x01,0x40,0x01,0xff]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
index 72cfc0b262a1c2..0ceac3da414ff3 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
@@ -3195,3 +3195,10 @@
0xfa,0x42,0xfe,0x7f,0xff,0x6f,0x3d,0x30
# GFX12: v_trunc_f32_dpp v255, -|v255| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0x42,0xfe,0x7f,0xff,0x6f,0x3d,0x30]
+
+0xfa,0x14,0x0a,0x7f,0x01,0x60,0x01,0x13
+# GFX12-FAKE16: v_mul_i32_i24_e32 v128, s1, v176 ; encoding: [0x01,0x60,0x01,0x13]
+# GFX12-REAL16: v_cvt_f16_f32_dpp v5.h, v1 row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x14,0x0a,0x7f,0x01,0x60,0x01,0x13]
+0xfa,0x16,0x0a,0x7e,0x81,0x60,0x01,0x13
+# GFX12-FAKE16: v_cvt_f32_f16_dpp v5, v129/*Invalid register, operand has 'VGPR_32_Lo128' register class*/ row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x16,0x0a,0x7e,0x81,0x60,0x01,0x13]
+# GFX12-REAL16: v_cvt_f32_f16_dpp v5, v1.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x16,0x0a,0x7e,0x81,0x60,0x01,0x13]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
index 0ab639082c38ea..4cd8b75a52f5af 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2.txt
@@ -2456,3 +2456,54 @@
0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf
# GFX12: v_xor_b32_e32 v255, 0xaf123456, v255 ; encoding: [0xff,0xfe,0xff,0x3b,0x56,0x34,0x12,0xaf]
+
+0x81,0x05,0x0a,0x76
+# GFX12-FAKE16: v_ldexp_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x76]
+# GFX12-REAL16: v_ldexp_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x76]
+0xff,0x05,0x0a,0x76
+# GFX12-FAKE16: v_ldexp_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x76]
+# GFX12-REAL16: v_ldexp_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x76]
+0xfd,0x04,0x0b,0x77
+# GFX12-REAL16: v_ldexp_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x77]
+0xff,0xfe,0xff,0x77,0x0b,0xfe,0x00,0x00
+# GFX12-REAL16: v_ldexp_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x77,0x0b,0xfe,0x00,0x00]
+0x81,0x05,0x0a,0x62
+# GFX12-FAKE16: v_max_num_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x62]
+# GFX12-REAL16: v_max_num_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x62]
+0xff,0x05,0x0a,0x62
+# GFX12-FAKE16: v_max_num_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x62]
+# GFX12-REAL16: v_max_num_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x62]
+0xfd,0x04,0x0b,0x63
+# GFX12-REAL16: v_max_num_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x63]
+0xff,0xfe,0xff,0x63,0x0b,0xfe,0x00,0x00
+# GFX12-REAL16: v_max_num_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x63,0x0b,0xfe,0x00,0x00]
+0x81,0x05,0x0a,0x60
+# GFX12-FAKE16: v_min_num_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x60]
+# GFX12-REAL16: v_min_num_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x60]
+0xff,0x05,0x0a,0x60
+# GFX12-FAKE16: v_min_num_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x60]
+# GFX12-REAL16: v_min_num_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x60]
+0xfd,0x04,0x0b,0x61
+# GFX12-REAL16: v_min_num_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x61]
+0xff,0xfe,0xff,0x61,0x0b,0xfe,0x00,0x00
+# GFX12-REAL16: v_min_num_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x61,0x0b,0xfe,0x00,0x00]
+0x81,0x05,0x0a,0x6a
+# GFX12-FAKE16: v_mul_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x6a]
+# GFX12-REAL16: v_mul_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x6a]
+0xff,0x05,0x0a,0x6a
+# GFX12-FAKE16: v_mul_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x6a]
+# GFX12-REAL16: v_mul_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x6a]
+0xfd,0x04,0x0b,0x6b
+# GFX12-REAL16: v_mul_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x6b]
+0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00
+# GFX12-REAL16: v_mul_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x6b,0x0b,0xfe,0x00,0x00]
+0x81,0x05,0x0a,0x68
+# GFX12-FAKE16: v_subrev_f16_e32 v5, v129/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0x81,0x05,0x0a,0x68]
+# GFX12-REAL16: v_subrev_f16_e32 v5.l, v1.h, v2.l ; encoding: [0x81,0x05,0x0a,0x68]
+0xff,0x05,0x0a,0x68
+# GFX12-FAKE16: v_subrev_f16_e32 v5, v255/*Invalid register, operand has 'VS_32_Lo128' register class*/, v2 ; encoding: [0xff,0x05,0x0a,0x68]
+# GFX12-REAL16: v_subrev_f16_e32 v5.l, v127.h, v2.l ; encoding: [0xff,0x05,0x0a,0x68]
+0xfd,0x04,0x0b,0x69
+# GFX12-REAL16: v_subrev_f16_e32 v5.h, src_scc, v2.h ; encoding: [0xfd,0x04,0x0b,0x69]
+0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00
+# GFX12-REAL16: v_subrev_f16_e32 v127.h, 0xfe0b, v127.h ; encoding: [0xff,0xfe,0xff,0x69,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
index 103cb2bd5ce4a5..22eda3ebad6ebb 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp16.txt
@@ -1833,3 +1833,34 @@
0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30
# GFX12: v_xor_b32_dpp v255, v255, v255 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x3b,0xff,0x6f,0x0d,0x30]
+
+0xfa,0x04,0x0b,0x77,0x81,0x60,0x01,0x13
+# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-REAL16: v_ldexp_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x77,0x81,0x60,0x01,0x13]
+0xfa,0xfe,0xff,0x77,0xff,0x6f,0x3d,0x30
+# GFX12-FAKE16: v_lshlrev_b32_e32 v30, v255, v183 ; encoding: [0xff,0x6f,0x3d,0x30]
+# GFX12-REAL16: v_ldexp_f16_dpp v127.h, -|v127.h|, v127.h row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x77,0xff,0x6f,0x3d,0x30]
+0xfa,0x04,0x0b,0x63,0x81,0x60,0x01,0x13
+# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-REAL16: v_max_num_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x63,0x81,0x60,0x01,0x13]
+0xfa,0xfe,0xff,0x63,0xff,0x6f,0xfd,0x30
+# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-REAL16: v_max_num_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x63,0xff,0x6f,0xfd,0x30]
+0xfa,0x04,0x0b,0x61,0x81,0x60,0x01,0x13
+# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-REAL16: v_min_num_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x61,0x81,0x60,0x01,0x13]
+0xfa,0xfe,0xff,0x61,0xff,0x6f,0xfd,0x30
+# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-REAL16: v_min_num_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x61,0xff,0x6f,0xfd,0x30]
+0xfa,0x04,0x0b,0x6b,0x81,0x60,0x01,0x13
+# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-REAL16: v_mul_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x6b,0x81,0x60,0x01,0x13]
+0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xfd,0x30
+# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-REAL16: v_mul_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x6b,0xff,0x6f,0xfd,0x30]
+0xfa,0x04,0x0b,0x69,0x81,0x60,0x01,0x13
+# GFX12-FAKE16: v_mul_i32_i24_e32 v128, 1, v176 ; encoding: [0x81,0x60,0x01,0x13]
+# GFX12-REAL16: v_subrev_f16_dpp v5.h, v1.h, v2.h row_xmask:0 row_mask:0x1 bank_mask:0x3 ; encoding: [0xfa,0x04,0x0b,0x69,0x81,0x60,0x01,0x13]
+0xfa,0xfe,0xff,0x69,0xff,0x6f,0xfd,0x30
+# GFX12-FAKE16: v_lshlrev_b32_e32 v126, v255, v183 ; encoding: [0xff,0x6f,0xfd,0x30]
+# GFX12-REAL16: v_subrev_f16_dpp v127.h, -|v127.h|, -|v127.h| row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xfa,0xfe,0xff,0x69,0xff,0x6f,0xfd,0x30]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
index ee1fc23e265f9b..2d2a7501552b2d 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop2_dpp8.txt
@@ -282,3 +282,29 @@
0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00
# GFX12: v_xor_b32_dpp v255, v255, v255 dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x3b,0xff,0x00,0x00,0x00]
+
+0xe9,0x04,0x0b,0x77,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-REAL16: v_ldexp_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x77,0x81,0x77,0x39,0x05]
+0xea,0xfe,0xff,0x77,0xff,0x00,0x00,0x00
+# GFX12-REAL16: v_ldexp_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x77,0xff,0x00,0x00,0x00]
+0xe9,0x04,0x0b,0x63,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-REAL16: v_max_num_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x63,0x81,0x77,0x39,0x05]
+0xea,0xfe,0xff,0x63,0xff,0x00,0x00,0x00
+# GFX12-REAL16: v_max_num_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x63,0xff,0x00,0x00,0x00]
+0xe9,0x04,0x0b,0x61,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-REAL16: v_min_num_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x61,0x81,0x77,0x39,0x05]
+0xea,0xfe,0xff,0x61,0xff,0x00,0x00,0x00
+# GFX12-REAL16: v_min_num_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x61,0xff,0x00,0x00,0x00]
+0xe9,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-REAL16: v_mul_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x6b,0x81,0x77,0x39,0x05]
+0xea,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00
+# GFX12-REAL16: v_mul_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x6b,0xff,0x00,0x00,0x00]
+0xe9,0x04,0x0b,0x69,0x81,0x77,0x39,0x05
+# GFX12-FAKE16: v_add_f64_e32 v[156:157], v[129:130], v[187:188] ; encoding: [0x81,0x77,0x39,0x05]
+# GFX12-REAL16: v_subrev_f16_dpp v5.h, v1.h, v2.h dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x04,0x0b,0x69,0x81,0x77,0x39,0x05]
+0xea,0xfe,0xff,0x69,0xff,0x00,0x00,0x00
+# GFX12-REAL16: v_subrev_f16_dpp v127.h, v127.h, v127.h dpp8:[0,0,0,0,0,0,0,0] fi:1 ; encoding: [0xea,0xfe,0xff,0x69,0xff,0x00,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
index 9cb456de1765ed..4b88869540f8a8 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
@@ -3868,3 +3868,67 @@
0xfe,0x80,0x97,0xd5,0xff,0x00,0x00,0x18,0x56,0x34,0x12,0xaf
# GFX12: v_trunc_f64_e64 v[254:255], 0xaf123456 clamp div:2 ; encoding: [0xfe,0x80,0x97,0xd5,0xff,0x00,0x01,0x1a,0x56,0x34,0x12,0xaf]
+
+0x05,0x48,0xdc,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_ceil_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_ceil_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xdc,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xdc,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_ceil_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_ceil_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xdc,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xdc,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_ceil_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xdc,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_ceil_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xdc,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+0x05,0x48,0xd8,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_exp_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xd8,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_exp_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xd8,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xd8,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_exp_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xd8,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_exp_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xd8,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xd8,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_exp_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd8,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_exp_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xd8,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+0x05,0x48,0xdb,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_floor_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xdb,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_floor_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xdb,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xdb,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_floor_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xdb,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_floor_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xdb,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xdb,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_floor_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xdb,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_floor_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xdb,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+0x05,0x48,0xd7,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_log_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xd7,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_log_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xd7,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xd7,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_log_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xd7,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_log_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xd7,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xd7,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_log_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd7,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_log_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xd7,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+0x05,0x48,0xd4,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_rcp_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xd4,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_rcp_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xd4,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xd4,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_rcp_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xd4,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_rcp_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xd4,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xd4,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_rcp_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd4,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_rcp_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xd4,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+0x05,0x48,0xd6,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_rsq_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xd6,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_rsq_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xd6,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xd6,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_rsq_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xd6,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_rsq_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xd6,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xd6,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_rsq_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd6,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_rsq_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xd6,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+0x05,0x48,0xd5,0xd5,0x01,0x01,0x00,0x00
+# GFX12-FAKE16: v_sqrt_f16_e64 v5, v1 ; encoding: [0x05,0x00,0xd5,0xd5,0x01,0x01,0x01,0x02]
+# GFX12-REAL16: v_sqrt_f16_e64 v5.h, v1.h op_sel:[1,1] ; encoding: [0x05,0x48,0xd5,0xd5,0x01,0x01,0x01,0x02]
+0x05,0x08,0xd5,0xd5,0xff,0x01,0x00,0x00
+# GFX12-FAKE16: v_sqrt_f16_e64 v5, v255 ; encoding: [0x05,0x00,0xd5,0xd5,0xff,0x01,0x01,0x02]
+# GFX12-REAL16: v_sqrt_f16_e64 v5.l, v255.h op_sel:[1,0] ; encoding: [0x05,0x08,0xd5,0xd5,0xff,0x01,0x01,0x02]
+0xff,0xc1,0xd5,0xd5,0xff,0x00,0x00,0x38,0x0b,0xfe,0x00,0x00
+# GFX12-FAKE16: v_sqrt_f16_e64 v255, -|0xfe0b| clamp div:2 ; encoding: [0xff,0x81,0xd5,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
+# GFX12-REAL16: v_sqrt_f16_e64 v255.h, -|0xfe0b| op_sel:[0,1] clamp div:2 ; encoding: [0xff,0xc1,0xd5,0xd5,0xff,0x00,0x01,0x3a,0x0b,0xfe,0x00,0x00]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
index fb9001347dff44..73cff7f18372f5 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
@@ -3077,3 +3077,67 @@
0xff,0x81,0xa1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30
# GFX12: v_trunc_f32_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:1 fi:1 ; encoding: [0xff,0x81,0xa1,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x0d,0x30]
+
+0x05,0x48,0xdc,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01
+# GFX12-FAKE16: v_ceil_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x00,0xdc,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+# GFX12-REAL16: v_ceil_f16_e64_dpp v5.h, v1.h op_sel:[1,1] mul:2 row_share:15 row_mask:0x0 bank_mask:0x1 ; encoding: [0x05,0x48,0xdc,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
+0x05,0x08,0...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/223825
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