[llvm-branch-commits] [llvm] [DAG][X86] Do not narrow trunc(select) to a type undesirable for SELECT (PR #223763)
Paweł Bylica via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 15 10:10:13 PDT 2026
https://github.com/chfast created https://github.com/llvm/llvm-project/pull/223763
DAGCombiner rewrites trunc(select c, a, b) as select c, (trunc a), (trunc b)
whenever truncating is free. On X86 that fires for i8, and where CMOV is
available there is no 8-bit form of it, so LowerSELECT widens the narrow select
back to i32 through ANY_EXTENDs, which lower to MOVZX. The narrowing then only
buys a byte ALU chain plus a MOVZX for each operand that became an i8 op:
orb $64, %al orl $64, %eax
movzbl %al, %eax cmovneq %rcx, %rax
cmovnel %ecx, %eax
Gate the fold on isTypeDesirableForOp(ISD::SELECT, VT) and let X86 report i8 as
undesirable when it can use CMOV. Without CMOV the select lowers to a branch
instead, where i8 operands are fine, so narrowing stays enabled there. The hook
defaults to isTypeLegal(VT), so guarded by isTypeLegal it is a no-op for every
target that does not override it. A select of two constants stays exempt: it
introduces no truncate of a computed value, so the narrow form is never worse.
Measured against an unpatched build of the same commit: 24 fewer instructions
across the affected tests with no configuration worse, and the no-CMOV targets
(i686, elfiamcu, -mattr=-cmov) are byte-identical to trunk.
Stacked on #223762, which pre-commits the tests.
Assisted-by: Claude Code
>From db6aed4991dd68002ef31aac41a84dd0e3186383 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pawe=C5=82=20Bylica?= <pawel at hepcolgum.band>
Date: Tue, 15 Sep 2026 18:58:22 +0200
Subject: [PATCH] [DAG][X86] Do not narrow trunc(select) to a type undesirable
for SELECT
DAGCombiner rewrites trunc(select c, a, b) as select c, (trunc a), (trunc b)
whenever truncating is free. On X86 that fires for i8, and where CMOV is
available there is no 8-bit form of it, so LowerSELECT widens the narrow select
back to i32 through ANY_EXTENDs, which lower to MOVZX. The narrowing then only
buys a byte ALU chain plus a MOVZX for each operand that became an i8 op:
orb $64, %al orl $64, %eax
movzbl %al, %eax cmovneq %rcx, %rax
cmovnel %ecx, %eax
Gate the fold on isTypeDesirableForOp(ISD::SELECT, VT) and let X86 report i8 as
undesirable when it can use CMOV. Without CMOV the select lowers to a branch
instead, where i8 operands are fine, so narrowing stays enabled there. The hook
defaults to isTypeLegal(VT), so guarded by isTypeLegal it is a no-op for every
target that does not override it. A select of two constants stays exempt: it
introduces no truncate of a computed value, so the narrow form is never worse.
Assisted-by: Claude Code
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 9 +-
llvm/lib/Target/X86/X86ISelLowering.cpp | 8 ++
llvm/test/CodeGen/X86/bit-manip-i128.ll | 123 ++++++++++--------
llvm/test/CodeGen/X86/freeze.ll | 21 ++-
llvm/test/CodeGen/X86/lea-opt2.ll | 16 +--
llvm/test/CodeGen/X86/select.ll | 6 +-
.../test/CodeGen/X86/shl-crash-on-legalize.ll | 2 +-
.../CodeGen/X86/trunc-select-narrowing.ll | 35 +++--
8 files changed, 121 insertions(+), 99 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index a829d7a34d5a6..8794f7f9bfa27 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -17772,8 +17772,15 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
}
// trunc (select c, a, b) -> select c, (trunc a), (trunc b)
+ // Do not narrow to a legal type the target considers undesirable for a
+ // select (e.g. i8 on X86, which has no 8-bit CMOV and would widen it again),
+ // unless both select operands are constants: then no truncate of a computed
+ // value is introduced and the narrow select is never worse.
if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse() &&
- TLI.isTruncateFree(SrcVT, VT)) {
+ TLI.isTruncateFree(SrcVT, VT) &&
+ (!TLI.isTypeLegal(VT) || TLI.isTypeDesirableForOp(ISD::SELECT, VT) ||
+ (isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true) &&
+ isConstantOrConstantVector(N0.getOperand(2), /*NoOpaques=*/true)))) {
if (!LegalOperations ||
(TLI.isOperationLegal(ISD::SELECT, SrcVT) &&
TLI.isNarrowingProfitable(N0.getNode(), SrcVT, VT))) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index de6745de05702..ce8b45b451763 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -64283,6 +64283,14 @@ bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
if ((Opc == ISD::MUL || Opc == ISD::SHL) && VT == MVT::i8)
return false;
+ // There is no 8-bit CMOV, so with CMOV available LowerSELECT widens an i8
+ // select to i32 through ANY_EXTENDs, which are not free (they lower to MOVZX
+ // to avoid partial register stalls). Narrowing a select to i8 therefore only
+ // adds instructions. Without CMOV the select becomes a branch instead and i8
+ // operands are fine, so keep it desirable there.
+ if (Opc == ISD::SELECT && VT == MVT::i8 && Subtarget.canUseCMOV())
+ return false;
+
// i16 instruction encodings are longer and some i16 instructions are slow,
// so those are not desirable.
if (VT == MVT::i16) {
diff --git a/llvm/test/CodeGen/X86/bit-manip-i128.ll b/llvm/test/CodeGen/X86/bit-manip-i128.ll
index 451ce3b1b7578..4672226db94fe 100644
--- a/llvm/test/CodeGen/X86/bit-manip-i128.ll
+++ b/llvm/test/CodeGen/X86/bit-manip-i128.ll
@@ -905,10 +905,9 @@ define i128 @isolate_msb_i128(i128 %a0, i128 %idx) nounwind {
; SSE-NEXT: xorl $63, %eax
; SSE-NEXT: bsrq %rdi, %rcx
; SSE-NEXT: xorl $63, %ecx
-; SSE-NEXT: orb $64, %cl
+; SSE-NEXT: orl $64, %ecx
; SSE-NEXT: testq %rsi, %rsi
-; SSE-NEXT: movzbl %cl, %ecx
-; SSE-NEXT: cmovnel %eax, %ecx
+; SSE-NEXT: cmovneq %rax, %rcx
; SSE-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: shrdq %cl, %rdx, %rax
@@ -925,10 +924,9 @@ define i128 @isolate_msb_i128(i128 %a0, i128 %idx) nounwind {
; AVX-LABEL: isolate_msb_i128:
; AVX: # %bb.0:
; AVX-NEXT: lzcntq %rdi, %rax
-; AVX-NEXT: addb $64, %al
-; AVX-NEXT: lzcntq %rsi, %rdx
-; AVX-NEXT: movzbl %al, %ecx
-; AVX-NEXT: cmovael %edx, %ecx
+; AVX-NEXT: addl $64, %eax
+; AVX-NEXT: lzcntq %rsi, %rcx
+; AVX-NEXT: cmovbq %rax, %rcx
; AVX-NEXT: xorl %r8d, %r8d
; AVX-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; AVX-NEXT: xorl %eax, %eax
@@ -954,19 +952,18 @@ define i128 @isolate_msb_i128_vector(<2 x i64> %v0, i128 %idx) nounwind {
; SSE2: # %bb.0:
; SSE2-NEXT: movq %xmm0, %rax
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; SSE2-NEXT: movq %xmm1, %rcx
+; SSE2-NEXT: movq %xmm1, %rdx
; SSE2-NEXT: pxor %xmm1, %xmm1
; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
; SSE2-NEXT: movmskps %xmm1, %esi
; SSE2-NEXT: xorl $15, %esi
-; SSE2-NEXT: bsrq %rcx, %rdx
-; SSE2-NEXT: xorl $63, %edx
-; SSE2-NEXT: bsrq %rax, %rax
-; SSE2-NEXT: xorl $63, %eax
-; SSE2-NEXT: orb $64, %al
-; SSE2-NEXT: testq %rcx, %rcx
-; SSE2-NEXT: movzbl %al, %ecx
-; SSE2-NEXT: cmovnel %edx, %ecx
+; SSE2-NEXT: bsrq %rdx, %rdi
+; SSE2-NEXT: xorl $63, %edi
+; SSE2-NEXT: bsrq %rax, %rcx
+; SSE2-NEXT: xorl $63, %ecx
+; SSE2-NEXT: orl $64, %ecx
+; SSE2-NEXT: testq %rdx, %rdx
+; SSE2-NEXT: cmovneq %rdi, %rcx
; SSE2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: shrdq %cl, %rdx, %rax
@@ -983,15 +980,14 @@ define i128 @isolate_msb_i128_vector(<2 x i64> %v0, i128 %idx) nounwind {
; SSE42-LABEL: isolate_msb_i128_vector:
; SSE42: # %bb.0:
; SSE42-NEXT: movq %xmm0, %rax
-; SSE42-NEXT: pextrq $1, %xmm0, %rcx
-; SSE42-NEXT: bsrq %rcx, %rdx
-; SSE42-NEXT: xorl $63, %edx
-; SSE42-NEXT: bsrq %rax, %rax
-; SSE42-NEXT: xorl $63, %eax
-; SSE42-NEXT: orb $64, %al
-; SSE42-NEXT: testq %rcx, %rcx
-; SSE42-NEXT: movzbl %al, %ecx
-; SSE42-NEXT: cmovnel %edx, %ecx
+; SSE42-NEXT: pextrq $1, %xmm0, %rdx
+; SSE42-NEXT: bsrq %rdx, %rsi
+; SSE42-NEXT: xorl $63, %esi
+; SSE42-NEXT: bsrq %rax, %rcx
+; SSE42-NEXT: xorl $63, %ecx
+; SSE42-NEXT: orl $64, %ecx
+; SSE42-NEXT: testq %rdx, %rdx
+; SSE42-NEXT: cmovneq %rsi, %rcx
; SSE42-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; SSE42-NEXT: xorl %eax, %eax
; SSE42-NEXT: shrdq %cl, %rdx, %rax
@@ -1005,27 +1001,48 @@ define i128 @isolate_msb_i128_vector(<2 x i64> %v0, i128 %idx) nounwind {
; SSE42-NEXT: cmoveq %rsi, %rdx
; SSE42-NEXT: retq
;
-; AVX-LABEL: isolate_msb_i128_vector:
-; AVX: # %bb.0:
-; AVX-NEXT: vpextrq $1, %xmm0, %rax
-; AVX-NEXT: vmovq %xmm0, %rcx
-; AVX-NEXT: lzcntq %rcx, %rcx
-; AVX-NEXT: addb $64, %cl
-; AVX-NEXT: lzcntq %rax, %rax
-; AVX-NEXT: movzbl %cl, %ecx
-; AVX-NEXT: cmovael %eax, %ecx
-; AVX-NEXT: xorl %esi, %esi
-; AVX-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: shrdq %cl, %rdx, %rax
-; AVX-NEXT: shrxq %rcx, %rdx, %rdx
-; AVX-NEXT: testb $64, %cl
-; AVX-NEXT: cmovneq %rdx, %rax
-; AVX-NEXT: cmovneq %rsi, %rdx
-; AVX-NEXT: vptest %xmm0, %xmm0
-; AVX-NEXT: cmoveq %rsi, %rax
-; AVX-NEXT: cmoveq %rsi, %rdx
-; AVX-NEXT: retq
+; AVX2-LABEL: isolate_msb_i128_vector:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpextrq $1, %xmm0, %rax
+; AVX2-NEXT: vmovq %xmm0, %rcx
+; AVX2-NEXT: lzcntq %rcx, %rdx
+; AVX2-NEXT: addl $64, %edx
+; AVX2-NEXT: xorl %ecx, %ecx
+; AVX2-NEXT: lzcntq %rax, %rcx
+; AVX2-NEXT: cmovbq %rdx, %rcx
+; AVX2-NEXT: xorl %esi, %esi
+; AVX2-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
+; AVX2-NEXT: xorl %eax, %eax
+; AVX2-NEXT: shrdq %cl, %rdx, %rax
+; AVX2-NEXT: shrxq %rcx, %rdx, %rdx
+; AVX2-NEXT: testb $64, %cl
+; AVX2-NEXT: cmovneq %rdx, %rax
+; AVX2-NEXT: cmovneq %rsi, %rdx
+; AVX2-NEXT: vptest %xmm0, %xmm0
+; AVX2-NEXT: cmoveq %rsi, %rax
+; AVX2-NEXT: cmoveq %rsi, %rdx
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: isolate_msb_i128_vector:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpextrq $1, %xmm0, %rax
+; AVX512-NEXT: vmovq %xmm0, %rcx
+; AVX512-NEXT: lzcntq %rcx, %rdx
+; AVX512-NEXT: addl $64, %edx
+; AVX512-NEXT: lzcntq %rax, %rcx
+; AVX512-NEXT: cmovbq %rdx, %rcx
+; AVX512-NEXT: xorl %esi, %esi
+; AVX512-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
+; AVX512-NEXT: xorl %eax, %eax
+; AVX512-NEXT: shrdq %cl, %rdx, %rax
+; AVX512-NEXT: shrxq %rcx, %rdx, %rdx
+; AVX512-NEXT: testb $64, %cl
+; AVX512-NEXT: cmovneq %rdx, %rax
+; AVX512-NEXT: cmovneq %rsi, %rdx
+; AVX512-NEXT: vptest %xmm0, %xmm0
+; AVX512-NEXT: cmoveq %rsi, %rax
+; AVX512-NEXT: cmoveq %rsi, %rdx
+; AVX512-NEXT: retq
%a0 = bitcast <2 x i64> %v0 to i128
%eqz = icmp eq i128 %a0, 0
%clz = call i128 @llvm.ctlz.i128(i128 %a0, i1 -1)
@@ -1044,10 +1061,9 @@ define i128 @isolate_msb_i128_load(ptr %p0, i128 %idx) nounwind {
; SSE-NEXT: xorl $63, %eax
; SSE-NEXT: bsrq %rsi, %rcx
; SSE-NEXT: xorl $63, %ecx
-; SSE-NEXT: orb $64, %cl
+; SSE-NEXT: orl $64, %ecx
; SSE-NEXT: testq %rdi, %rdi
-; SSE-NEXT: movzbl %cl, %ecx
-; SSE-NEXT: cmovnel %eax, %ecx
+; SSE-NEXT: cmovneq %rax, %rcx
; SSE-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; SSE-NEXT: xorl %eax, %eax
; SSE-NEXT: shrdq %cl, %rdx, %rax
@@ -1066,10 +1082,9 @@ define i128 @isolate_msb_i128_load(ptr %p0, i128 %idx) nounwind {
; AVX-NEXT: movq (%rdi), %rsi
; AVX-NEXT: movq 8(%rdi), %rdi
; AVX-NEXT: lzcntq %rsi, %rax
-; AVX-NEXT: addb $64, %al
-; AVX-NEXT: lzcntq %rdi, %rdx
-; AVX-NEXT: movzbl %al, %ecx
-; AVX-NEXT: cmovael %edx, %ecx
+; AVX-NEXT: addl $64, %eax
+; AVX-NEXT: lzcntq %rdi, %rcx
+; AVX-NEXT: cmovbq %rax, %rcx
; AVX-NEXT: xorl %r8d, %r8d
; AVX-NEXT: movabsq $-9223372036854775808, %rdx # imm = 0x8000000000000000
; AVX-NEXT: xorl %eax, %eax
@@ -1557,5 +1572,3 @@ define i128 @bitreverse_i128_load(ptr %p0) nounwind {
ret i128 %res
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; AVX512: {{.*}}
diff --git a/llvm/test/CodeGen/X86/freeze.ll b/llvm/test/CodeGen/X86/freeze.ll
index 38e3e23f7caac..9568ac981b8f3 100644
--- a/llvm/test/CodeGen/X86/freeze.ll
+++ b/llvm/test/CodeGen/X86/freeze.ll
@@ -149,20 +149,19 @@ define i64 @pr155345(ptr %p1, i1 %cond, ptr %p2, ptr %p3) {
; X86ASM: # %bb.0: # %entry
; X86ASM-NEXT: movzbl (%rdi), %edi
; X86ASM-NEXT: xorl %eax, %eax
-; X86ASM-NEXT: orb $1, %dil
+; X86ASM-NEXT: orq $1, %rdi
; X86ASM-NEXT: movb %dil, (%rdx)
-; X86ASM-NEXT: movzbl %dil, %edx
-; X86ASM-NEXT: cmovel %edx, %eax
-; X86ASM-NEXT: sete %dil
+; X86ASM-NEXT: cmoveq %rdi, %rax
+; X86ASM-NEXT: sete %dl
; X86ASM-NEXT: testb $1, %sil
-; X86ASM-NEXT: cmovnel %edx, %eax
-; X86ASM-NEXT: movb %dl, (%rcx)
-; X86ASM-NEXT: movl $1, %edx
+; X86ASM-NEXT: cmovneq %rdi, %rax
+; X86ASM-NEXT: movb %dil, (%rcx)
+; X86ASM-NEXT: movl $1, %edi
; X86ASM-NEXT: movl %eax, %ecx
-; X86ASM-NEXT: shlq %cl, %rdx
-; X86ASM-NEXT: orb %sil, %dil
-; X86ASM-NEXT: movzbl %dil, %eax
-; X86ASM-NEXT: andl %edx, %eax
+; X86ASM-NEXT: shlq %cl, %rdi
+; X86ASM-NEXT: orb %sil, %dl
+; X86ASM-NEXT: movzbl %dl, %eax
+; X86ASM-NEXT: andl %edi, %eax
; X86ASM-NEXT: andl $1, %eax
; X86ASM-NEXT: retq
entry:
diff --git a/llvm/test/CodeGen/X86/lea-opt2.ll b/llvm/test/CodeGen/X86/lea-opt2.ll
index f7588577a3e9a..b1c69dcc02669 100644
--- a/llvm/test/CodeGen/X86/lea-opt2.ll
+++ b/llvm/test/CodeGen/X86/lea-opt2.ll
@@ -213,17 +213,17 @@ define void @test10() {
; CHECK-LABEL: test10:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl (%rax), %eax
-; CHECK-NEXT: movzwl (%rax), %ecx
-; CHECK-NEXT: leal (%rcx,%rcx,2), %esi
-; CHECK-NEXT: movl %ecx, %edi
-; CHECK-NEXT: subl %ecx, %edi
-; CHECK-NEXT: subl %ecx, %edi
-; CHECK-NEXT: negl %esi
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpl $4, %eax
-; CHECK-NEXT: movl %edi, (%rax)
-; CHECK-NEXT: movl %esi, (%rax)
; CHECK-NEXT: cmovnel %eax, %ecx
+; CHECK-NEXT: movzwl (%rax), %eax
+; CHECK-NEXT: leal (%rax,%rax), %edx
+; CHECK-NEXT: leal (%rax,%rax,2), %esi
+; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: subl %edx, %eax
+; CHECK-NEXT: movl %eax, (%rax)
+; CHECK-NEXT: negl %esi
+; CHECK-NEXT: movl %esi, (%rax)
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: sarl %cl, %esi
; CHECK-NEXT: movl %esi, (%rax)
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
index 1901ba9408e91..50bf87c17b8e5 100644
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -1297,7 +1297,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; GENERIC-NEXT: movl $127, %eax
; GENERIC-NEXT: cmovlel %edi, %eax
; GENERIC-NEXT: cmpl $-128, %eax
-; GENERIC-NEXT: movl $128, %ecx
+; GENERIC-NEXT: movl $-128, %ecx
; GENERIC-NEXT: cmovgel %eax, %ecx
; GENERIC-NEXT: movb %cl, (%rsi)
; GENERIC-NEXT: retq
@@ -1306,7 +1306,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; ATOM: ## %bb.0:
; ATOM-NEXT: cmpl $127, %edi
; ATOM-NEXT: movl $127, %eax
-; ATOM-NEXT: movl $128, %ecx
+; ATOM-NEXT: movl $-128, %ecx
; ATOM-NEXT: cmovlel %edi, %eax
; ATOM-NEXT: cmpl $-128, %eax
; ATOM-NEXT: cmovgel %eax, %ecx
@@ -1321,7 +1321,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; ATHLON-NEXT: movl $127, %edx
; ATHLON-NEXT: cmovlel %ecx, %edx
; ATHLON-NEXT: cmpl $-128, %edx
-; ATHLON-NEXT: movl $128, %ecx
+; ATHLON-NEXT: movl $-128, %ecx
; ATHLON-NEXT: cmovgel %edx, %ecx
; ATHLON-NEXT: movb %cl, (%eax)
; ATHLON-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll b/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
index 5f21a23f257a8..c518f8ad7e942 100644
--- a/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
+++ b/llvm/test/CodeGen/X86/shl-crash-on-legalize.ll
@@ -17,7 +17,7 @@ define i32 @PR29058(i8 %x, i32 %y) {
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: cmpb $1, %dil
; CHECK-NEXT: sbbl %ecx, %ecx
-; CHECK-NEXT: orb %sil, %cl
+; CHECK-NEXT: orl %esi, %ecx
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: movq %rax, structMember(%rip)
diff --git a/llvm/test/CodeGen/X86/trunc-select-narrowing.ll b/llvm/test/CodeGen/X86/trunc-select-narrowing.ll
index 73dffa7ef1848..9ea554db15ed1 100644
--- a/llvm/test/CodeGen/X86/trunc-select-narrowing.ll
+++ b/llvm/test/CodeGen/X86/trunc-select-narrowing.ll
@@ -16,11 +16,10 @@ define i8 @trunc_select_add_i64(i64 %x, i64 %y) nounwind {
; X64-NEXT: xorl $63, %ecx
; X64-NEXT: bsrq %rsi, %rax
; X64-NEXT: xorl $63, %eax
-; X64-NEXT: orb $64, %al
+; X64-NEXT: orl $64, %eax
; X64-NEXT: testq %rdi, %rdi
-; X64-NEXT: movzbl %al, %eax
-; X64-NEXT: cmovnel %ecx, %eax
-; X64-NEXT: # kill: def $al killed $al killed $eax
+; X64-NEXT: cmovneq %rcx, %rax
+; X64-NEXT: # kill: def $al killed $al killed $rax
; X64-NEXT: retq
;
; X86-CMOV-LABEL: trunc_select_add_i64:
@@ -114,24 +113,22 @@ define i8 @trunc_select_add_i32(i32 %x, i32 %y) nounwind {
; X64-NEXT: xorl $31, %ecx
; X64-NEXT: bsrl %esi, %eax
; X64-NEXT: xorl $31, %eax
-; X64-NEXT: orb $32, %al
+; X64-NEXT: orl $32, %eax
; X64-NEXT: testl %edi, %edi
-; X64-NEXT: movzbl %al, %eax
; X64-NEXT: cmovnel %ecx, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-CMOV-LABEL: trunc_select_add_i32:
; X86-CMOV: # %bb.0:
-; X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-CMOV-NEXT: bsrl %eax, %ecx
-; X86-CMOV-NEXT: xorl $31, %ecx
-; X86-CMOV-NEXT: bsrl {{[0-9]+}}(%esp), %edx
+; X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-CMOV-NEXT: bsrl %ecx, %edx
; X86-CMOV-NEXT: xorl $31, %edx
-; X86-CMOV-NEXT: orb $32, %dl
-; X86-CMOV-NEXT: testl %eax, %eax
-; X86-CMOV-NEXT: movzbl %dl, %eax
-; X86-CMOV-NEXT: cmovnel %ecx, %eax
+; X86-CMOV-NEXT: bsrl {{[0-9]+}}(%esp), %eax
+; X86-CMOV-NEXT: xorl $31, %eax
+; X86-CMOV-NEXT: orl $32, %eax
+; X86-CMOV-NEXT: testl %ecx, %ecx
+; X86-CMOV-NEXT: cmovnel %edx, %eax
; X86-CMOV-NEXT: # kill: def $al killed $al killed $eax
; X86-CMOV-NEXT: retl
;
@@ -198,20 +195,18 @@ define i8 @trunc_select_constants(i32 %x) nounwind {
define i8 @trunc_select_one_constant(i32 %x, i32 %y) nounwind {
; X64-LABEL: trunc_select_one_constant:
; X64: # %bb.0:
-; X64-NEXT: orb $64, %sil
+; X64-NEXT: orl $64, %esi
; X64-NEXT: testl %edi, %edi
-; X64-NEXT: movzbl %sil, %ecx
; X64-NEXT: movl $11, %eax
-; X64-NEXT: cmovnel %ecx, %eax
+; X64-NEXT: cmovnel %esi, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; X86-CMOV-LABEL: trunc_select_one_constant:
; X86-CMOV: # %bb.0:
-; X86-CMOV-NEXT: movzbl {{[0-9]+}}(%esp), %eax
-; X86-CMOV-NEXT: orb $64, %al
+; X86-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-CMOV-NEXT: orl $64, %ecx
; X86-CMOV-NEXT: cmpl $0, {{[0-9]+}}(%esp)
-; X86-CMOV-NEXT: movzbl %al, %ecx
; X86-CMOV-NEXT: movl $11, %eax
; X86-CMOV-NEXT: cmovnel %ecx, %eax
; X86-CMOV-NEXT: # kill: def $al killed $al killed $eax
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