[llvm-branch-commits] [llvm] [AMDGPU] Add BarrierLatency mutations to CoexecSched (PR #200954)

[Quentin Colombet via llvm-branch-commits]

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@@ -0,0 +1,171 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=COEXEC %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched --amdgpu-barrier-signal-wait-latency=0 %s -o - | FileCheck -check-prefix=COEXEC-LAT-0 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched --amdgpu-barrier-signal-wait-latency=30 %s -o - | FileCheck -check-prefix=COEXEC-LAT-30 %s
+
+--- |
+  define void @test-sched-signal-wait() #0 { ret void }
+
+  attributes #0 = { "amdgpu-waves-per-eu"="1,1" }
+...
+
+---
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qcolombet wrote:

Could you highlight with a short comment in the test what there is to see here?

https://github.com/llvm/llvm-project/pull/200954