[llvm-branch-commits] [llvm] [AMDGPU] Fix register class for a few isel patterns (PR #219733)

[Matt Arsenault via llvm-branch-commits]

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@@ -2429,29 +2429,35 @@ let OtherPredicates = [HasPackedD16VMem,HasMTBUFInsts] in {
 } // End HasPackedD16VMem,HasMTBUFInsts.
 
 multiclass MTBUF_StoreIntrinsicPat_Common<SDPatternOperator name, ValueType vt,
-                                        string opcode, ValueType memoryVt = vt> {
+                                        string opcode, ValueType memoryVt = vt, bit isTrue16 = false> {
   defvar st = !if(!eq(memoryVt, vt), name, mtbuf_intrinsic_store<name, memoryVt>);
 
   def : GCNPat<
     (st vt:$vdata, v4i32:$rsrc, 0, 0, (BUFSOffset i32:$soffset), timm:$offset,
           timm:$format, timm:$auxiliary, 0),
-    (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) getVregSrcForVT<vt>.ret:$vdata, SReg_128:$rsrc, SCSrc_b32:$soffset,
+    (!cast<MTBUF_Pseudo>(opcode # _OFFSET_exact) 
+      !if(isTrue16, (lo16_to_vgpr32 $vdata), (vt getVregSrcForVT<vt>.ret:$vdata)),
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arsenm wrote:

Can you sink the true16 check into getVregSrcForVT

https://github.com/llvm/llvm-project/pull/219733