[llvm-branch-commits] [llvm] [AMDGPU] Fold sreg32 operand across Lo16 subcopy (PR #217999)

[Matt Arsenault via llvm-branch-commits]

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@@ -935,6 +935,24 @@ bool SIFoldOperandsImpl::tryAddToFoldList(
       }
     }
 
+    // Special case for valu16 using sreg32
+    // %1:vgpr32 = copy %0:sreg32/sregxx:sub_x
+    // VALU16 %1.lo16:vgpr16 ...
+    // =>
+    // VALU16 %0:sreg32/sregxx:sub_x...
+    // Hack to allow 32-bit SGPRs to be folded into True16 instructions
+    // Remove this if 16-bit SGPRs (i.e. SGPR_LO16) are added to the
+    // VS_16RegClass
+    if (OpToFold.isReg() && OpToFold.DefSubReg == AMDGPU::lo16 &&
+        TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
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arsenm wrote:

you can more directly check against isSubclassEq of SReg_32 

https://github.com/llvm/llvm-project/pull/217999