[llvm-branch-commits] [llvm] [AMDGPU] Fold sreg32 operand across Lo16 subcopy (PR #217999)

[Matt Arsenault via llvm-branch-commits]

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@@ -1538,6 +1556,45 @@ bool SIFoldOperandsImpl::foldOperand(
         return true;
     }
 
+    // Look through Lo16 Copy
+    // OpToFold: %0
+    // %1:vgpr32 = copy %0:sreg32/sregxx:sub_x
+    // %2:vgpr16 = copy %1.lo16:vgpr32  (UseMI)
+    // VALU16 %2:vgpr16 ...
+    // =>
+    // VALU16 %0:sreg32/sregxx:sub_x...
+    // Hack to allow 32-bit SGPRs to be folded into True16 instructions
+    // Remove this if 16-bit SGPRs (i.e. SGPR_LO16) are added to the
+    // VS_16RegClass
+    if (UseMI->isCopy() && OpToFold.isReg() &&
+        UseMI->getOperand(0).getReg().isVirtual() &&
+        TRI->isSGPRReg(*MRI, OpToFold.getReg()) &&
+        TII->getOpSize(*UseMI, 0) == 2 &&
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arsenm wrote:

Avoid size based logic and check register class + subreg compatibility 

https://github.com/llvm/llvm-project/pull/217999