[llvm-branch-commits] [llvm] [AMDGPU] Apply occupancy-aware register allocation anti-hints (PR #218074)

[Matt Arsenault via llvm-branch-commits]

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@@ -4225,22 +4225,56 @@ bool SIRegisterInfo::shouldApplyAntiHints(
   return true;
 }
 
+// Returns true if Reg fits within the current occupancy VGPR budget.
+bool SIRegisterInfo::isRegWithinOccupancyBudget(
+    MCPhysReg Reg, unsigned NumVGPRs, unsigned NumAGPRs,
+    unsigned MaxVGPRsForCurrentOccupancy) const {
+  const TargetRegisterClass *RC = getPhysRegBaseClass(Reg);
+
+  // No VGPR or AGPR usage.
+  if (!RC || (!isVGPRClass(RC) && !isAGPRClass(RC)))
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arsenm wrote:

hasVectorRegisters(RC)?

https://github.com/llvm/llvm-project/pull/218074