[llvm-branch-commits] [llvm] [NFC][LICM] Pre-commit tests for loop-invariant store AA (PR #222685)
Zach Goldthorpe via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Sep 11 07:07:35 PDT 2026
https://github.com/zGoldthorpe updated https://github.com/llvm/llvm-project/pull/222685
>From 128b9ea1d474c4549ecc5842eb1f6515b5373b65 Mon Sep 17 00:00:00 2001
From: Zach Goldthorpe <Zach.Goldthorpe at amd.com>
Date: Tue, 8 Sep 2026 14:57:49 -0500
Subject: [PATCH] [NFC][LICM] Pre-commit tests for loop-invariant store AA
---
.../Transforms/LICM/scalar-promote-aa-tags.ll | 427 ++++++++++++++++++
1 file changed, 427 insertions(+)
create mode 100644 llvm/test/Transforms/LICM/scalar-promote-aa-tags.ll
diff --git a/llvm/test/Transforms/LICM/scalar-promote-aa-tags.ll b/llvm/test/Transforms/LICM/scalar-promote-aa-tags.ll
new file mode 100644
index 0000000000000..ae6340ab51263
--- /dev/null
+++ b/llvm/test/Transforms/LICM/scalar-promote-aa-tags.ll
@@ -0,0 +1,427 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -aa-pipeline=tbaa,scoped-noalias-aa,basic-aa -passes='require<aa>,require<target-ir>,require<scalar-evolution>,require<opt-remark-emit>,loop-mssa(licm)' -S %s | FileCheck %s
+
+declare i32 @opaque(i32) memory(argmem: readwrite)
+
+define i32 @promotable.store_dominates_exit_block(i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @promotable.store_dominates_exit_block(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0:![0-9]+]]
+; CHECK-NEXT: [[V_INC:%.*]] = add i32 [[V]], 1
+; CHECK-NEXT: store i32 [[V_INC]], ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4:![0-9]+]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[LATCH]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %v = load i32, ptr %ptr, !tbaa !0
+ %v.inc = add i32 %v, 1
+ store i32 %v.inc, ptr %ptr, !tbaa !0
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ br i1 %c, label %if, label %latch
+
+if:
+ store i32 0, ptr %ptr, !tbaa !0
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @not_promotable.store_does_not_dominate_exit_block(i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @not_promotable.store_does_not_dominate_exit_block(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[LATCH]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: [[V_INC:%.*]] = add i32 [[V]], 1
+; CHECK-NEXT: store i32 [[V_INC]], ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ br i1 %c, label %if, label %latch
+
+if:
+ %v = load i32, ptr %ptr, !tbaa !0
+ %v.inc = add i32 %v, 1
+ store i32 %v.inc, ptr %ptr, !tbaa !0
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @not_promotable.store_dominates_only_one_exit_block(i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @not_promotable.store_dominates_only_one_exit_block(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4]]
+; CHECK-NEXT: br i1 [[C]], label %[[BODY:.*]], label %[[EARLY_EXIT:.*]]
+; CHECK: [[BODY]]:
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: [[V_INC:%.*]] = add i32 [[V]], 1
+; CHECK-NEXT: store i32 [[V_INC]], ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EARLY_EXIT]]:
+; CHECK-NEXT: ret i32 0
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ br i1 %c, label %body, label %early.exit
+
+body:
+ %v = load i32, ptr %ptr, !tbaa !0
+ %v.inc = add i32 %v, 1
+ store i32 %v.inc, ptr %ptr, !tbaa !0
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+early.exit:
+ ret i32 0
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @promotable.stores_jointly_dominate_exit_blocks(i64 %idx, i1 %c, i1 %c2, i1 %c3) {
+; CHECK-LABEL: define i32 @promotable.stores_jointly_dominate_exit_blocks(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]], i1 [[C3:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[ELSE:.*]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: store i32 1, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LATCH]]
+; CHECK: [[ELSE]]:
+; CHECK-NEXT: store i32 2, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br i1 [[C3]], label %[[EXIT]], label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ br i1 %c, label %if, label %else
+
+if:
+ store i32 1, ptr %ptr, !tbaa !0
+ br i1 %c2, label %exit, label %latch
+
+else:
+ store i32 2, ptr %ptr, !tbaa !0
+ br i1 %c3, label %exit, label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @not_promotable.dominating_stores_with_different_tags(i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @not_promotable.dominating_stores_with_different_tags(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: [[V_INC:%.*]] = add i32 [[V]], 1
+; CHECK-NEXT: store i32 [[V_INC]], ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[LATCH]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4, !tbaa [[UNSIGNED_INT_TBAA6:![0-9]+]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ %v = load i32, ptr %ptr, !tbaa !0
+ %v.inc = add i32 %v, 1
+ store i32 %v.inc, ptr %ptr, !tbaa !0
+ br i1 %c, label %if, label %latch
+
+if:
+ store i32 0, ptr %ptr, !tbaa !9
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @promotable.dominating_store_with_unwind(i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @promotable.dominating_store_with_unwind(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4]]
+; CHECK-NEXT: [[T:%.*]] = call i32 @opaque(i32 1)
+; CHECK-NEXT: store i32 [[T]], ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[LATCH]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ %t = call i32 @opaque(i32 1)
+ store i32 %t, ptr %ptr, !tbaa !0
+ br i1 %c, label %if, label %latch
+
+if:
+ store i32 0, ptr %ptr, !tbaa !0
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @promotable.noalias_store_dominates_exit_block(i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @promotable.noalias_store_dominates_exit_block(
+; CHECK-SAME: i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[PTR:%.*]] = alloca [4 x i32], align 4
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store i32 42, ptr [[FPTR]], align 4, !alias.scope [[META8:![0-9]+]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[PTR]], align 4, !noalias [[META8]]
+; CHECK-NEXT: [[V_INC:%.*]] = add i32 [[V]], 1
+; CHECK-NEXT: store i32 [[V_INC]], ptr [[PTR]], align 4, !noalias [[META8]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[LATCH]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4, !noalias [[META8]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ %ptr = alloca [4 x i32]
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr i32, ptr %ptr, i64 %iv
+ store i32 42, ptr %fptr, !alias.scope !8
+ %v = load i32, ptr %ptr, !noalias !8
+ %v.inc = add i32 %v, 1
+ store i32 %v.inc, ptr %ptr, !noalias !8
+ br i1 %c, label %if, label %latch
+
+if:
+ store i32 0, ptr %ptr, !noalias !8
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+define i32 @promotable.store_dominates_exit_block_non_thread_local_ptr(ptr %ptr, i64 %idx, i1 %c, i1 %c2) {
+; CHECK-LABEL: define i32 @promotable.store_dominates_exit_block_non_thread_local_ptr(
+; CHECK-SAME: ptr [[PTR:%.*]], i64 [[IDX:%.*]], i1 [[C:%.*]], i1 [[C2:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IDX]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LATCH:.*]] ]
+; CHECK-NEXT: [[FPTR:%.*]] = getelementptr float, ptr [[PTR]], i64 [[IV]]
+; CHECK-NEXT: store float 0.000000e+00, ptr [[FPTR]], align 4, !tbaa [[FLOAT_TBAA4]]
+; CHECK-NEXT: [[V:%.*]] = load i32, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: [[V_INC:%.*]] = add i32 [[V]], 1
+; CHECK-NEXT: store i32 [[V_INC]], ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br i1 [[C]], label %[[IF:.*]], label %[[LATCH]]
+; CHECK: [[IF]]:
+; CHECK-NEXT: store i32 0, ptr [[PTR]], align 4, !tbaa [[INT_TBAA0]]
+; CHECK-NEXT: br label %[[LATCH]]
+; CHECK: [[LATCH]]:
+; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
+; CHECK-NEXT: br i1 [[C2]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[PTR]], align 4
+; CHECK-NEXT: ret i32 [[RES]]
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ %idx, %entry ], [ %iv.next, %latch ]
+ %fptr = getelementptr float, ptr %ptr, i64 %iv
+ store float 0.000000e+00, ptr %fptr, !tbaa !3
+ %v = load i32, ptr %ptr, !tbaa !0
+ %v.inc = add i32 %v, 1
+ store i32 %v.inc, ptr %ptr, !tbaa !0
+ br i1 %c, label %if, label %latch
+
+if:
+ store i32 0, ptr %ptr, !tbaa !0
+ br label %latch
+
+latch:
+ %iv.next = add i64 %iv, 1
+ br i1 %c2, label %exit, label %loop
+
+exit:
+ %res = load i32, ptr %ptr
+ ret i32 %res
+}
+
+!0 = !{!4, !4, i64 0}
+!1 = !{!"omnipotent char", !2}
+!2 = !{!"Simple C/C++ TBAA"}
+!3 = !{!5, !5, i64 0}
+!4 = !{!"int", !1}
+!5 = !{!"float", !1}
+!6 = !{!6}
+!7 = !{!7, !6}
+!8 = !{!7}
+!9 = !{!10, !10, i64 0}
+!10 = !{!"unsigned int", !1}
+;.
+; CHECK: [[INT_TBAA0]] = !{[[META1:![0-9]+]], [[META1]], i64 0}
+; CHECK: [[META1]] = !{!"int", [[META2:![0-9]+]]}
+; CHECK: [[META2]] = !{!"omnipotent char", [[META3:![0-9]+]]}
+; CHECK: [[META3]] = !{!"Simple C/C++ TBAA"}
+; CHECK: [[FLOAT_TBAA4]] = !{[[META5:![0-9]+]], [[META5]], i64 0}
+; CHECK: [[META5]] = !{!"float", [[META2]]}
+; CHECK: [[UNSIGNED_INT_TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
+; CHECK: [[META7]] = !{!"unsigned int", [[META2]]}
+; CHECK: [[META8]] = !{[[META9:![0-9]+]]}
+; CHECK: [[META9]] = distinct !{[[META9]], [[META10:![0-9]+]]}
+; CHECK: [[META10]] = distinct !{[[META10]]}
+;.
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