[llvm-branch-commits] [clang] [llvm] [HLSL] Add `InterlockedCompareStoreFloatBitwise` function and resource methods (PR #222166)
Joshua Batista via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Sep 9 13:04:04 PDT 2026
https://github.com/bob80905 updated https://github.com/llvm/llvm-project/pull/222166
>From 55cbf6dbcb180fd30ef7459894ccd390a54928d7 Mon Sep 17 00:00:00 2001
From: Joshua Batista <jbatista at microsoft.com>
Date: Tue, 8 Sep 2026 13:36:59 -0700
Subject: [PATCH] First attempt implementing
InterlockedCompareStoreFloatBitwise
---
clang/include/clang/Basic/Builtins.td | 9 ++
clang/lib/CodeGen/CGHLSLBuiltins.cpp | 14 ++-
clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp | 5 +
clang/lib/Sema/HLSLExternalSemaSource.cpp | 17 ++-
clang/lib/Sema/SemaHLSL.cpp | 28 +++--
.../InterlockedCompareStoreFloatBitwise.hlsl | 35 ++++++
.../builtins/RWBuffer-Interlocked.hlsl | 6 ++
...r-InterlockedCompareStoreFloatBitwise.hlsl | 27 +++++
...r-InterlockedCompareStoreFloatBitwise.hlsl | 21 ++++
...erlockedCompareStoreFloatBitwise-sm60.hlsl | 39 +++++++
...lockedCompareStoreFloatBitwise-errors.hlsl | 100 ++++++++++++++++++
.../ResourceAtomicCompareStoreFloat.ll | 30 ++++++
12 files changed, 318 insertions(+), 13 deletions(-)
create mode 100644 clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
create mode 100644 clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
create mode 100644 clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
create mode 100644 clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
create mode 100644 clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
create mode 100644 llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td
index c07cffbe4ebae..189d17173b055 100644
--- a/clang/include/clang/Basic/Builtins.td
+++ b/clang/include/clang/Basic/Builtins.td
@@ -5575,6 +5575,15 @@ def HLSLInterlockedCompareStore : LangBuiltin<"HLSL_LANG"> {
let Prototype = "void (...)";
}
+def HLSLInterlockedCompareStoreFloatBitwise : LangBuiltin<"HLSL_LANG"> {
+ let Spellings = ["__builtin_hlsl_interlocked_compare_store_float_bitwise"];
+ // SemaHLSL checks these arguments itself. Custom type checking also stops
+ // the default variadic promotion, which would otherwise widen the float
+ // arguments to double.
+ let Attributes = [NoThrow, CustomTypeChecking];
+ let Prototype = "void (...)";
+}
+
def HLSLInterlockedExchange : LangBuiltin<"HLSL_LANG"> {
let Spellings = ["__builtin_hlsl_interlocked_exchange"];
// SemaHLSL checks these arguments itself. Custom type checking also stops
diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp
index 80835f6f27f2f..65cc094c69d4f 100644
--- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp
+++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp
@@ -358,6 +358,17 @@ static Value *handleInterlockedCompareOp(CodeGenFunction &CGF,
Value *Compare = CGF.EmitScalarExpr(E->getArg(1));
Value *Val = CGF.EmitScalarExpr(E->getArg(2));
+ // `cmpxchg` takes an integer or a pointer, so the float-bitwise operations
+ // work on the bit pattern of the float. This is what those operations mean,
+ // and DXIL and SPIR-V both need the integer form.
+ if (Compare->getType()->isFloatingPointTy()) {
+ llvm::Type *IntTy =
+ CGF.Builder.getIntNTy(Compare->getType()->getPrimitiveSizeInBits());
+ Compare = CGF.Builder.CreateBitCast(Compare, IntTy);
+ Val = CGF.Builder.CreateBitCast(Val, IntTy);
+ DestAddr = DestAddr.withElementType(IntTy);
+ }
+
Value *Pair = CGF.Builder.CreateAtomicCmpXchg(
DestAddr, Compare, Val, llvm::AtomicOrdering::Monotonic,
llvm::AtomicOrdering::Monotonic, getHLSLAtomicScope(CGF, DestLV));
@@ -1516,7 +1527,8 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
return handleInterlockedOp(*this, E, llvm::AtomicRMWInst::And);
}
case Builtin::BI__builtin_hlsl_interlocked_compare_exchange:
- case Builtin::BI__builtin_hlsl_interlocked_compare_store: {
+ case Builtin::BI__builtin_hlsl_interlocked_compare_store:
+ case Builtin::BI__builtin_hlsl_interlocked_compare_store_float_bitwise: {
return handleInterlockedCompareOp(*this, E);
}
case Builtin::BI__builtin_hlsl_interlocked_exchange: {
diff --git a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
index 3c374f8649c55..9918a09338482 100644
--- a/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
+++ b/clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp
@@ -1760,6 +1760,11 @@ BuiltinTypeDeclBuilder::addByteAddressBufferInterlockedMethods() {
addByteAddressBufferInterlockedCompareMethod(
"InterlockedCompareStore", AST.UnsignedIntTy,
"__builtin_hlsl_interlocked_compare_store");
+ // The float-bitwise compare reuses the 32-bit integer DXIL operation, so it
+ // needs no capability bits and works from SM 6.0.
+ addByteAddressBufferInterlockedCompareMethod(
+ "InterlockedCompareStoreFloatBitwise", AST.FloatTy,
+ "__builtin_hlsl_interlocked_compare_store_float_bitwise");
addByteAddressBufferInterlockedMethod(
"InterlockedExchange", AST.UnsignedIntTy,
"__builtin_hlsl_interlocked_exchange", /*RequiresOriginalValue=*/true);
diff --git a/clang/lib/Sema/HLSLExternalSemaSource.cpp b/clang/lib/Sema/HLSLExternalSemaSource.cpp
index 13539c421b8e0..5c949a184dcd8 100644
--- a/clang/lib/Sema/HLSLExternalSemaSource.cpp
+++ b/clang/lib/Sema/HLSLExternalSemaSource.cpp
@@ -925,15 +925,20 @@ static void defineHLSLInterlockedFunc(Sema &S, NamespaceDecl *NS,
// Synthesize the compare-and-swap overload sets: {int, uint, int64_t,
// uint64_t} x {groupshared, device}. Compare-store reports nothing and
// compare-exchange always reports the previous value, so each has a single
-// arity. The float forms are separate intrinsics.
+// arity. The float-bitwise operations carry their own names and take float
+// alone, so they get a float-only overload set.
static void defineHLSLInterlockedCompareFunc(Sema &S, NamespaceDecl *NS,
StringRef FuncName,
StringRef BuiltinName,
- AtomicOverloadShape Shape) {
+ AtomicOverloadShape Shape,
+ bool FloatOnly = false) {
ASTContext &AST = S.getASTContext();
// HLSL: int64_t == long, uint64_t == unsigned long (see hlsl_basic_types.h).
- QualType Elems[] = {AST.IntTy, AST.UnsignedIntTy, AST.LongTy,
- AST.UnsignedLongTy};
+ QualType IntElems[] = {AST.IntTy, AST.UnsignedIntTy, AST.LongTy,
+ AST.UnsignedLongTy};
+ QualType FloatElems[] = {AST.FloatTy};
+ ArrayRef<QualType> Elems =
+ FloatOnly ? ArrayRef<QualType>(FloatElems) : ArrayRef<QualType>(IntElems);
for (QualType ElemTy : Elems)
for (LangAS AS : {LangAS::hlsl_groupshared, LangAS::hlsl_device})
@@ -953,6 +958,10 @@ void HLSLExternalSemaSource::defineHLSLAtomicIntrinsics() {
"InterlockedCompareStore",
"__builtin_hlsl_interlocked_compare_store",
AtomicOverloadShape::CompareStore);
+ defineHLSLInterlockedCompareFunc(
+ *SemaPtr, HLSLNamespace, "InterlockedCompareStoreFloatBitwise",
+ "__builtin_hlsl_interlocked_compare_store_float_bitwise",
+ AtomicOverloadShape::CompareStore, /*FloatOnly=*/true);
defineHLSLInterlockedFunc(*SemaPtr, HLSLNamespace, "InterlockedExchange",
"__builtin_hlsl_interlocked_exchange",
/*RequiresOriginalValue=*/true,
diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp
index bde8e806b5b82..4ac2cb458bd41 100644
--- a/clang/lib/Sema/SemaHLSL.cpp
+++ b/clang/lib/Sema/SemaHLSL.cpp
@@ -4714,6 +4714,7 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
case Builtin::BI__builtin_hlsl_interlocked_and:
case Builtin::BI__builtin_hlsl_interlocked_compare_exchange:
case Builtin::BI__builtin_hlsl_interlocked_compare_store:
+ case Builtin::BI__builtin_hlsl_interlocked_compare_store_float_bitwise:
case Builtin::BI__builtin_hlsl_interlocked_exchange:
case Builtin::BI__builtin_hlsl_interlocked_max:
case Builtin::BI__builtin_hlsl_interlocked_min:
@@ -4727,9 +4728,14 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
// on `dest`. The checks below are a safety net for callers that invoke the
// builtin by its mangled name and would otherwise reach CodeGen unchecked.
// InterlockedCompareStore takes `compare_value` and `value`, so its third
- // argument is an input rather than an output.
+ // argument is an input rather than an output. The float-bitwise form has
+ // the same shape and compares the bit patterns instead of the values.
+ const bool IsCompareStoreFloat =
+ BuiltinID ==
+ Builtin::BI__builtin_hlsl_interlocked_compare_store_float_bitwise;
const bool IsCompareStore =
- BuiltinID == Builtin::BI__builtin_hlsl_interlocked_compare_store;
+ BuiltinID == Builtin::BI__builtin_hlsl_interlocked_compare_store ||
+ IsCompareStoreFloat;
// InterlockedCompareExchange adds `compare_value` before `value` and
// always reports the previous value, so it takes four arguments.
const bool IsCompareExchange =
@@ -4756,16 +4762,22 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
}
QualType DestTy = TheCall->getArg(0)->getType().getUnqualifiedType();
- // InterlockedExchange also operates on float. DXIL lowers that as a
- // bitwise exchange of the value's bit pattern, and DXC accepts 32-bit
- // float only, so half and double are rejected.
+ // InterlockedExchange also operates on float, and the float-bitwise
+ // compare operations operate on float alone. DXIL lowers both as
+ // operations on the value's bit pattern, and DXC accepts 32-bit float
+ // only, so half and double are rejected.
+ const bool RequiresFloat = IsCompareStoreFloat;
const bool AllowsFloat =
+ RequiresFloat ||
BuiltinID == Builtin::BI__builtin_hlsl_interlocked_exchange;
- if (!DestTy->isIntegerType() &&
- !(AllowsFloat && DestTy->isSpecificBuiltinType(BuiltinType::Float))) {
+ const bool DestIsOK = DestTy->isSpecificBuiltinType(BuiltinType::Float)
+ ? AllowsFloat
+ : !RequiresFloat && DestTy->isIntegerType();
+ if (!DestIsOK) {
SemaRef.Diag(TheCall->getArg(0)->getBeginLoc(),
diag::err_builtin_invalid_arg_type)
- << /*ordinal=*/1 << /*scalar*/ 1 << /*integer*/ 1
+ << /*ordinal=*/1 << /*scalar*/ 1
+ << /*integer*/ (RequiresFloat ? 0 : 1)
<< /*32 bit floating-point*/ (AllowsFloat ? 3 : 0) << DestTy;
return true;
}
diff --git a/clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl b/clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
new file mode 100644
index 0000000000000..c5fbb4854e85c
--- /dev/null
+++ b/clang/test/CodeGenHLSL/builtins/InterlockedCompareStoreFloatBitwise.hlsl
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.6-library %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,DXCHECK
+
+// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \
+// RUN: spirv-pc-vulkan-library %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,SPVCHECK
+
+// Test basic lowering of HLSL InterlockedCompareStoreFloatBitwise to `cmpxchg
+// monotonic`. `cmpxchg` takes an integer, so the float arguments become their
+// bit patterns first. The operation reports nothing, so the `cmpxchg` result
+// stays unused.
+
+groupshared float gs_f32;
+
+// CHECK-LABEL: define {{.*}}void @{{.*}}test_float
+// CHECK: [[CMP:%.*]] = bitcast float %{{.*}} to i32
+// CHECK-NEXT: [[VAL:%.*]] = bitcast float %{{.*}} to i32
+// DXCHECK-NEXT: cmpxchg ptr addrspace(3) {{.*}}@gs_f32{{.*}}, i32 [[CMP]], i32 [[VAL]] syncscope("workgroup") monotonic monotonic
+// SPVCHECK-NEXT: cmpxchg ptr addrspace(3) {{.*}}@gs_f32{{.*}}, i32 [[CMP]], i32 [[VAL]] syncscope("workgroup") monotonic monotonic
+export void test_float(float cmp, float v) {
+ InterlockedCompareStoreFloatBitwise(gs_f32, cmp, v);
+}
+
+// A device-address-space destination uses the "device" scope instead.
+RWBuffer<float> Buf : register(u0);
+
+// CHECK-LABEL: define {{.*}}void @{{.*}}test_device
+// CHECK: [[CMP:%.*]] = bitcast float %{{.*}} to i32
+// CHECK-NEXT: [[VAL:%.*]] = bitcast float %{{.*}} to i32
+// DXCHECK-NEXT: cmpxchg ptr %{{.*}}, i32 [[CMP]], i32 [[VAL]] syncscope("device") monotonic monotonic
+// SPVCHECK-NEXT: cmpxchg ptr addrspace(11) %{{.*}}, i32 [[CMP]], i32 [[VAL]] syncscope("device") monotonic monotonic
+export void test_device(float cmp, float v) {
+ InterlockedCompareStoreFloatBitwise(Buf[0], cmp, v);
+}
diff --git a/clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl b/clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
index 47cff714a7df7..b85e40a9b1093 100644
--- a/clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
+++ b/clang/test/CodeGenHLSL/builtins/RWBuffer-Interlocked.hlsl
@@ -19,6 +19,7 @@
RWBuffer<int> Out : register(u0);
RWBuffer<uint> UOut : register(u1);
+RWBuffer<float> FOut : register(u2);
// CHECK-LABEL: define void @main
// DXCHECK: %[[PTR1:.*]] = call {{.*}} @llvm.dx.resource.getpointer.p0.tdx.TypedBuffer_i32_1_0_1t.i32(target("dx.TypedBuffer", i32, 1, 0, 1) %{{.*}}, i32 %{{.*}})
@@ -43,6 +44,8 @@ RWBuffer<uint> UOut : register(u1);
// DXCHECK: cmpxchg ptr %[[PTR10]], i32 1, i32 2 syncscope("device") monotonic monotonic
// DXCHECK: %[[PTR11:.*]] = call {{.*}} @llvm.dx.resource.getpointer.p0.tdx.TypedBuffer_i32_1_0_1t.i32(target("dx.TypedBuffer", i32, 1, 0, 1) %{{.*}}, i32 %{{.*}})
// DXCHECK: cmpxchg ptr %[[PTR11]], i32 1, i32 2 syncscope("device") monotonic monotonic
+// DXCHECK: %[[PTR12:.*]] = call {{.*}} @llvm.dx.resource.getpointer.p0.tdx.TypedBuffer_f32_1_0_0t.i32(target("dx.TypedBuffer", float, 1, 0, 0) %{{.*}}, i32 %{{.*}})
+// DXCHECK: cmpxchg ptr %[[PTR12]], i32 1065353216, i32 1073741824 syncscope("device") monotonic monotonic
// SPVCHECK: %[[PTR1:.*]] = call {{.*}} @llvm.spv.resource.getpointer.{{.*}}(target("spirv.SignedImage", i32, {{.*}}) %{{.*}}, i32 %{{.*}})
// SPVCHECK: atomicrmw add ptr addrspace(11) %[[PTR1]], i32 1 syncscope("device") monotonic
// SPVCHECK: %[[PTR2:.*]] = call {{.*}} @llvm.spv.resource.getpointer.{{.*}}(target("spirv.SignedImage", i32, {{.*}}) %{{.*}}, i32 %{{.*}})
@@ -65,6 +68,8 @@ RWBuffer<uint> UOut : register(u1);
// SPVCHECK: cmpxchg ptr addrspace(11) %[[PTR10]], i32 1, i32 2 syncscope("device") monotonic monotonic
// SPVCHECK: %[[PTR11:.*]] = call {{.*}} @llvm.spv.resource.getpointer.{{.*}}(target("spirv.SignedImage", i32, {{.*}}) %{{.*}}, i32 %{{.*}})
// SPVCHECK: cmpxchg ptr addrspace(11) %[[PTR11]], i32 1, i32 2 syncscope("device") monotonic monotonic
+// SPVCHECK: %[[PTR12:.*]] = call {{.*}} @llvm.spv.resource.getpointer.{{.*}}(target("spirv.Image", float, {{.*}}) %{{.*}}, i32 %{{.*}})
+// SPVCHECK: cmpxchg ptr addrspace(11) %[[PTR12]], i32 1065353216, i32 1073741824 syncscope("device") monotonic monotonic
[shader("compute")]
[numthreads(1,1,1)]
void main(uint3 id : SV_DispatchThreadID) {
@@ -80,4 +85,5 @@ void main(uint3 id : SV_DispatchThreadID) {
InterlockedExchange(Out[id.x], 1, orig);
InterlockedCompareStore(Out[id.x], 1, 2);
InterlockedCompareExchange(Out[id.x], 1, 2, orig);
+ InterlockedCompareStoreFloatBitwise(FOut[id.x], 1.0f, 2.0f);
}
diff --git a/clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl b/clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
new file mode 100644
index 0000000000000..ca2f2b02cdaa4
--- /dev/null
+++ b/clang/test/CodeGenHLSL/builtins/RWByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
@@ -0,0 +1,27 @@
+// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.6-library %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,DXCHECK
+
+// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple \
+// RUN: spirv-pc-vulkan1.3-library %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,SPVCHECK
+
+// Test that the RWByteAddressBuffer::InterlockedCompareStoreFloatBitwise
+// member method lowers to `resource_getpointer -> cmpxchg`, for both DXIL and
+// SPIR-V targets. The float arguments become their bit patterns first, because
+// `cmpxchg` takes an integer.
+
+RWByteAddressBuffer BAB : register(u0);
+
+// CHECK-LABEL: define {{.*}}void @{{.*}}test_bab_float
+// DXCHECK: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 0), ptr {{.*}}
+// DXCHECK: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_0t.i32(target("dx.RawBuffer", i8, 1, 0) %[[HANDLE]], i32 %{{.*}})
+// SPVCHECK: %[[HANDLE:.*]] = load target("spirv.VulkanBuffer", [0 x i8], 12, 1), ptr {{.*}}
+// SPVCHECK: %[[PTR:.*]] = call ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0i8_12_1t.i32(target("spirv.VulkanBuffer", [0 x i8], 12, 1) %[[HANDLE]], i32 %{{.*}})
+// CHECK: %[[CMP:.*]] = bitcast float %{{.*}} to i32
+// CHECK-NEXT: %[[VAL:.*]] = bitcast float %{{.*}} to i32
+// DXCHECK-NEXT: cmpxchg ptr %[[PTR]], i32 %[[CMP]], i32 %[[VAL]] syncscope("device") monotonic monotonic
+// SPVCHECK-NEXT: cmpxchg ptr addrspace(11) %[[PTR]], i32 %[[CMP]], i32 %[[VAL]] syncscope("device") monotonic monotonic
+export void test_bab_float(uint off, float cmp, float v) {
+ BAB.InterlockedCompareStoreFloatBitwise(off, cmp, v);
+}
diff --git a/clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl b/clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
new file mode 100644
index 0000000000000..5ddc6a4956f15
--- /dev/null
+++ b/clang/test/CodeGenHLSL/builtins/RasterizerOrderedByteAddressBuffer-InterlockedCompareStoreFloatBitwise.hlsl
@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header -triple \
+// RUN: dxil-pc-shadermodel6.6-library %s -emit-llvm -disable-llvm-passes -o - | \
+// RUN: FileCheck %s --check-prefixes=CHECK,DXCHECK
+
+// SPIR-V codegen for RasterizerOrderedByteAddressBuffer is not implemented
+// yet (asserts in clang/lib/CodeGen/Targets/SPIR.cpp on
+// `!ResAttrs.IsROV && "Rasterizer order views not implemented for SPIR-V yet"`).
+// Add a `spirv-pc-vulkan1.3-library` RUN line here when SPIR-V ROV support
+// lands.
+
+RasterizerOrderedByteAddressBuffer ROVB : register(u1);
+
+// CHECK-LABEL: define void @{{.*}}test_rovb_float
+// DXCHECK: %[[HANDLE:.*]] = load target("dx.RawBuffer", i8, 1, 1), ptr {{.*}}
+// DXCHECK: %[[PTR:.*]] = call ptr @llvm.dx.resource.getpointer.p0.tdx.RawBuffer_i8_1_1t.i32(target("dx.RawBuffer", i8, 1, 1) %[[HANDLE]], i32 %{{.*}})
+// DXCHECK: %[[CMP:.*]] = bitcast float %{{.*}} to i32
+// DXCHECK-NEXT: %[[VAL:.*]] = bitcast float %{{.*}} to i32
+// DXCHECK-NEXT: cmpxchg ptr %[[PTR]], i32 %[[CMP]], i32 %[[VAL]] syncscope("device") monotonic monotonic
+export void test_rovb_float(uint off, float cmp, float v) {
+ ROVB.InterlockedCompareStoreFloatBitwise(off, cmp, v);
+}
diff --git a/clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl b/clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
new file mode 100644
index 0000000000000..5954884163670
--- /dev/null
+++ b/clang/test/SemaHLSL/BuiltIns/ByteAddressBuffer-InterlockedCompareStoreFloatBitwise-sm60.hlsl
@@ -0,0 +1,39 @@
+// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header \
+// RUN: -triple dxil-pc-shadermodel6.0-library %s -fsyntax-only -verify \
+// RUN: -verify-ignore-unexpected=warning
+
+// The float-bitwise compare reuses the 32-bit integer DXIL operation, so it
+// needs no capability bits and works from SM 6.0. The 64-bit compare-store
+// needs SM 6.6. This file checks both halves, so it proves the two are gated
+// differently.
+
+RWByteAddressBuffer BAB : register(u0);
+RasterizerOrderedByteAddressBuffer ROVB : register(u1);
+groupshared float gs_f32;
+groupshared uint64_t gs_u64;
+
+void sm60_bab_float_bitwise_ok(uint off, float cmp, float v) {
+ BAB.InterlockedCompareStoreFloatBitwise(off, cmp, v);
+}
+
+void sm60_rovb_float_bitwise_ok(uint off, float cmp, float v) {
+ ROVB.InterlockedCompareStoreFloatBitwise(off, cmp, v);
+}
+
+void sm60_free_function_ok(float cmp, float v) {
+ InterlockedCompareStoreFloatBitwise(gs_f32, cmp, v);
+}
+
+void sm60_direct_builtin_ok(float cmp, float v) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_f32, cmp, v);
+}
+
+void sm60_no_bab_compare_store64(uint off, uint64_t cmp, uint64_t v) {
+ BAB.InterlockedCompareStore64(off, cmp, v);
+ // expected-error at -1 {{no member named 'InterlockedCompareStore64' in 'hlsl::RWByteAddressBuffer'}}
+}
+
+void sm60_no_direct_builtin_u64(uint64_t cmp, uint64_t v) {
+ __builtin_hlsl_interlocked_compare_store(gs_u64, cmp, v);
+ // expected-error at -1 {{'__builtin_hlsl_interlocked_compare_store' requires shader model 6.6 or newer}}
+}
diff --git a/clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
new file mode 100644
index 0000000000000..f291c6264f099
--- /dev/null
+++ b/clang/test/SemaHLSL/BuiltIns/InterlockedCompareStoreFloatBitwise-errors.hlsl
@@ -0,0 +1,100 @@
+// RUN: %clang_cc1 -std=hlsl202x -finclude-default-header \
+// RUN: -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only \
+// RUN: -disable-llvm-passes -verify
+
+// InterlockedCompareStoreFloatBitwise compares the bit pattern of a 32-bit
+// float, so it is provided as a float-only overload set (groupshared/device).
+// It reports nothing, so it has a single 3-argument form and no out parameter.
+
+groupshared float gs_f32;
+groupshared int gs_i32;
+groupshared double gs_f64;
+groupshared half gs_f16;
+struct S { float x; };
+groupshared S gs_s;
+
+void too_few(float cmp) {
+ InterlockedCompareStoreFloatBitwise(gs_f32, cmp); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+void too_many(float cmp, float v, float extra) {
+ InterlockedCompareStoreFloatBitwise(gs_f32, cmp, v, extra); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+void local_dest(float cmp, float v) {
+ float dest;
+ InterlockedCompareStoreFloatBitwise(dest, cmp, v); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+// The bitwise compare is defined for 32-bit float alone, so there is no
+// integer, half or double overload.
+void int_dest(int cmp, int v) {
+ InterlockedCompareStoreFloatBitwise(gs_i32, cmp, v); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+void double_dest(double cmp, double v) {
+ InterlockedCompareStoreFloatBitwise(gs_f64, cmp, v); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+void half_dest(half cmp, half v) {
+ InterlockedCompareStoreFloatBitwise(gs_f16, cmp, v); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+void struct_dest(float cmp, float v) {
+ InterlockedCompareStoreFloatBitwise(gs_s, cmp, v); // expected-error{{no matching function for call to 'InterlockedCompareStoreFloatBitwise'}}
+ // expected-note@*:* 2 {{candidate function}}
+}
+
+void direct_too_few(float cmp) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_f32, cmp);
+ // expected-error at -1 {{too few arguments to function call, expected 3, have 2}}
+}
+
+void direct_too_many(float cmp, float v, float extra) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_f32, cmp, v, extra);
+ // expected-error at -1 {{too many arguments to function call, expected 3, have 4}}
+}
+
+void direct_integer_dest(int cmp, int v) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_i32, cmp, v);
+ // expected-error at -1 {{1st argument must be a scalar 32 bit floating-point type (was 'int')}}
+}
+
+void direct_double_dest(double cmp, double v) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_f64, cmp, v);
+ // expected-error at -1 {{1st argument must be a scalar 32 bit floating-point type (was 'double')}}
+}
+
+void direct_half_dest(half cmp, half v) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_f16, cmp, v);
+ // expected-error at -1 {{1st argument must be a scalar 32 bit floating-point type (was 'half')}}
+}
+
+void direct_non_scalar_dest() {
+ S local_s;
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(local_s, 1.0f, 2.0f);
+ // expected-error at -1 {{1st argument must be a scalar 32 bit floating-point type (was 'S')}}
+}
+
+void direct_nonlvalue_dest(float cmp, float v) {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(1.0f, cmp, v);
+ // expected-error at -1 {{cannot bind non-lvalue argument '1.F' to out parameter}}
+}
+
+void direct_default_as_dest(float cmp, float v) {
+ float local;
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(local, cmp, v);
+ // expected-error at -1 {{1st argument to atomic builtin must reference groupshared or device memory (was 'float')}}
+}
+
+// The last argument is the new value rather than an out parameter, so an
+// rvalue is accepted here.
+void direct_rvalue_value_ok() {
+ __builtin_hlsl_interlocked_compare_store_float_bitwise(gs_f32, 1.0f, 2.0f);
+}
diff --git a/llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll b/llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
new file mode 100644
index 0000000000000..d544976f4e129
--- /dev/null
+++ b/llvm/test/CodeGen/DirectX/ResourceAtomicCompareStoreFloat.ll
@@ -0,0 +1,30 @@
+; RUN: opt -S -dxil-resource-access -dxil-op-lower -mtriple=dxil-pc-shadermodel6.6-compute %s | FileCheck %s
+
+; InterlockedCompareStoreFloatBitwise compares the bit pattern of a float, so
+; clang emits an i32 `cmpxchg` on a float resource. Lowering must key the DXIL
+; op off the operand type rather than the resource element type.
+
+target triple = "dxil-pc-shadermodel6.6-compute"
+
+; CHECK-LABEL: define void @typed_buffer_float_compare_store
+define void @typed_buffer_float_compare_store(i32 %index, i32 %cmp, i32 %val) {
+ %buffer = call target("dx.TypedBuffer", float, 1, 0, 0)
+ @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, ptr null)
+ %ptr = call ptr @llvm.dx.resource.getpointer(
+ target("dx.TypedBuffer", float, 1, 0, 0) %buffer, i32 %index)
+ ; CHECK: call i32 @dx.op.atomicCompareExchange.i32(i32 79, %dx.types.Handle %{{.*}}, i32 %index, i32 poison, i32 0, i32 %cmp, i32 %val)
+ %old = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic
+ ret void
+}
+
+; The raw buffer path carries no element type, so the same i32 op applies.
+; CHECK-LABEL: define void @raw_buffer_float_compare_store
+define void @raw_buffer_float_compare_store(i32 %offset, i32 %cmp, i32 %val) {
+ %buffer = call target("dx.RawBuffer", i8, 1, 0, 0)
+ @llvm.dx.resource.handlefrombinding(i32 0, i32 0, i32 1, i32 0, ptr null)
+ %ptr = call ptr @llvm.dx.resource.getpointer(
+ target("dx.RawBuffer", i8, 1, 0, 0) %buffer, i32 %offset)
+ ; CHECK: call i32 @dx.op.atomicCompareExchange.i32(i32 79, %dx.types.Handle %{{.*}}, i32 %offset, i32 poison, i32 0, i32 %cmp, i32 %val)
+ %old = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic
+ ret void
+}
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