[llvm-branch-commits] [llvm] llvm: Remove phantom relocation-model attributes from tests (PR #221931)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/221931

>From 6390ccd4366535691f5cd32ddee5484c28971020 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 8 Sep 2026 11:10:11 +0200
Subject: [PATCH] llvm: Remove phantom relocation-model attributes from tests

"relocation-model" was never a real function attribute.

Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
---
 llvm/test/CodeGen/AArch64/arm64-abi_align.ll         | 8 ++++----
 llvm/test/CodeGen/AMDGPU/loop-address.ll             | 2 +-
 llvm/test/CodeGen/Hexagon/insert4.ll                 | 2 +-
 llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll         | 2 +-
 llvm/test/CodeGen/Hexagon/vect/vect-xor.ll           | 2 +-
 llvm/test/Transforms/LoopVectorize/dbg.value.ll      | 2 +-
 llvm/test/Transforms/LoopVectorize/vectorize-once.ll | 2 +-
 llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll | 4 ++--
 8 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
index e664ccdc94f56..4a36721a91e25 100644
--- a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll
@@ -507,10 +507,10 @@ entry:
   ret i32 %call
 }
 
-attributes #0 = { noinline nounwind readnone "relocation-model"="pic" }
-attributes #1 = { nounwind readonly "relocation-model"="pic" }
-attributes #2 = { noinline nounwind readonly "relocation-model"="pic" }
-attributes #3 = { nounwind "relocation-model"="pic" }
+attributes #0 = { noinline nounwind readnone }
+attributes #1 = { nounwind readonly }
+attributes #2 = { noinline nounwind readonly }
+attributes #3 = { nounwind }
 attributes #4 = { nounwind }
 attributes #5 = { nobuiltin }
 
diff --git a/llvm/test/CodeGen/AMDGPU/loop-address.ll b/llvm/test/CodeGen/AMDGPU/loop-address.ll
index 59caabc8c0378..7fbcc8ab4edd3 100644
--- a/llvm/test/CodeGen/AMDGPU/loop-address.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop-address.ll
@@ -24,7 +24,7 @@ for.end:                                          ; preds = %for.body, %entry
   ret void
 }
 
-attributes #0 = { nounwind "relocation-model"="pic" }
+attributes #0 = { nounwind }
 
 !opencl.kernels = !{!0, !1, !2, !3}
 
diff --git a/llvm/test/CodeGen/Hexagon/insert4.ll b/llvm/test/CodeGen/Hexagon/insert4.ll
index de8242fb6b2ab..1122b39870366 100644
--- a/llvm/test/CodeGen/Hexagon/insert4.ll
+++ b/llvm/test/CodeGen/Hexagon/insert4.ll
@@ -103,7 +103,7 @@ declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1
 
 declare i64 @llvm.hexagon.A2.vaddhs(i64, i64) #1
 
-attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" }
+attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" }
 attributes #1 = { nounwind readnone }
 
 !0 = !{!"short", !1}
diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
index 471b3bc75459d..bbace671e47cf 100644
--- a/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-v4i16.ll
@@ -67,4 +67,4 @@ polly.stmt.for.body29:                            ; preds = %polly.stmt.for.body
   br i1 %exitcond, label %for.end.loopexit, label %polly.stmt.for.body29
 }
 
-attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" }
+attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" }
diff --git a/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll b/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
index 4faebbc7c3f86..e4b1e09729d8e 100644
--- a/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
+++ b/llvm/test/CodeGen/Hexagon/vect/vect-xor.ll
@@ -34,4 +34,4 @@ polly.loop_body:                                  ; preds = %entry, %polly.loop_
   br i1 %0, label %polly.loop_body, label %polly.loop_after
 }
 
-attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="static" }
+attributes #0 = { nounwind "frame-pointer"="non-leaf" "realign-stack" }
diff --git a/llvm/test/Transforms/LoopVectorize/dbg.value.ll b/llvm/test/Transforms/LoopVectorize/dbg.value.ll
index b16b1f8d729a5..0c4ee3067cd80 100644
--- a/llvm/test/Transforms/LoopVectorize/dbg.value.ll
+++ b/llvm/test/Transforms/LoopVectorize/dbg.value.ll
@@ -35,7 +35,7 @@ for.end:
 }
 
 
-attributes #0 = { "frame-pointer"="non-leaf" "relocation-model"="pic" }
+attributes #0 = { "frame-pointer"="non-leaf" }
 
 !llvm.dbg.cu = !{!11}
 !llvm.module.flags = !{!14}
diff --git a/llvm/test/Transforms/LoopVectorize/vectorize-once.ll b/llvm/test/Transforms/LoopVectorize/vectorize-once.ll
index 7095c1a8f26fa..ad96baa0d6126 100644
--- a/llvm/test/Transforms/LoopVectorize/vectorize-once.ll
+++ b/llvm/test/Transforms/LoopVectorize/vectorize-once.ll
@@ -67,7 +67,7 @@ _ZSt10accumulateIPiiET0_T_S2_S1_.exit:
   ret i32 %__init.addr.0.lcssa.i
 }
 
-attributes #0 = { nounwind readonly ssp uwtable "frame-pointer"="non-leaf" "realign-stack" "relocation-model"="pic" }
+attributes #0 = { nounwind readonly ssp uwtable "frame-pointer"="non-leaf" "realign-stack" }
 
 ; CHECK:      [[VEC_LOOP1]] = distinct !{[[VEC_LOOP1]], [[MD_IS_VEC:![0-9]+]], [[MD_RT_UNROLL_DIS:![0-9]+]]}
 ; CHECK-NEXT: [[MD_IS_VEC:![0-9]+]] = !{!"llvm.loop.isvectorized", i32 1}
diff --git a/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll b/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
index abd00fc37fc5b..09d606ff09294 100644
--- a/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
+++ b/llvm/test/Transforms/SimplifyCFG/volatile-phioper.ll
@@ -57,8 +57,8 @@ end:
 }
 declare i32 @Trace(...) #1
 
-attributes #0 = { nounwind ssp uwtable "frame-pointer"="non-leaf" "relocation-model"="pic" }
-attributes #1 = { "frame-pointer"="non-leaf" "relocation-model"="pic" }
+attributes #0 = { nounwind ssp uwtable "frame-pointer"="non-leaf" }
+attributes #1 = { "frame-pointer"="non-leaf" }
 attributes #2 = { nounwind }
 
 !0 = !{i32 1039}