[llvm-branch-commits] [llvm] [AMDGPU] Add FUNC_WAVE32 for object linking info flag (PR #207633)
Shilei Tian via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Sep 6 19:26:19 PDT 2026
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/207633
>From f0549249297f0111f3a6af7a80aeabf2ab291035 Mon Sep 17 00:00:00 2001
From: Shilei Tian <i at tianshilei.me>
Date: Sat, 4 Jul 2026 18:45:38 -0400
Subject: [PATCH] [AMDGPU] Add FUNC_WAVE32 for object linking info flag
---
llvm/docs/AMDGPUUsage.rst | 1 +
.../llvm/Support/AMDGPUObjLinkingInfo.h | 4 +-
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 1 +
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 1 +
.../MCTargetDesc/AMDGPUTargetStreamer.cpp | 4 ++
.../MCTargetDesc/AMDGPUTargetStreamer.h | 1 +
.../CodeGen/AMDGPU/lds-link-time-codegen.ll | 56 ++++++++++++-------
llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s | 10 ++--
8 files changed, 52 insertions(+), 26 deletions(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 689b988346612..72233350e6fb8 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -3469,6 +3469,7 @@ if needed.
0x2 ``FUNC_USES_FLAT_SCRATCH`` Function uses flat scratch addressing
0x4 ``FUNC_HAS_DYN_STACK`` Function has dynamic stack allocation
0x8 ``FUNC_FULL_SIMD_MODE`` Function uses full SIMD execution mode
+ 0x10 ``FUNC_WAVE32`` Function uses wave32; otherwise wave64
===== =========================== ==========================================
Symbol references (``INFO_FUNC``, ``INFO_USE``, ``INFO_CALL``) generate
diff --git a/llvm/include/llvm/Support/AMDGPUObjLinkingInfo.h b/llvm/include/llvm/Support/AMDGPUObjLinkingInfo.h
index 5c8cac56e8fb6..7c7fb6f6fe7e4 100644
--- a/llvm/include/llvm/Support/AMDGPUObjLinkingInfo.h
+++ b/llvm/include/llvm/Support/AMDGPUObjLinkingInfo.h
@@ -70,7 +70,9 @@ enum class FuncInfoFlags : uint32_t {
FUNC_HAS_DYN_STACK = 1U << 2,
/// Function uses full SIMD mode. If unset, the function uses half SIMD mode.
FUNC_FULL_SIMD_MODE = 1U << 3,
- LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/FUNC_FULL_SIMD_MODE),
+ /// Function uses wave32. If unset, the function uses wave64.
+ FUNC_WAVE32 = 1U << 4,
+ LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/FUNC_WAVE32),
};
} // namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 08226496b18ad..b3fb897a3f73f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -966,6 +966,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
/*PrivateSegmentSize=*/static_cast<uint32_t>(RU.PrivateSegmentSize),
/*Occupancy=*/Occupancy,
/*UsesFullSIMDMode=*/AMDGPU::isFullSIMDMode(STM),
+ /*UsesWave32=*/STM.getWavefrontSize() == 32,
/*UsesVCC=*/RU.UsesVCC,
/*UsesFlatScratch=*/RU.UsesFlatScratch,
/*HasDynStack=*/RU.HasDynamicallySizedStack,
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index a7e19fcec62bd..05a44684f1d8c 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -6985,6 +6985,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPUInfo() {
FI.HasDynStack = !!(Flags & AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK);
FI.UsesFullSIMDMode =
!!(Flags & AMDGPU::FuncInfoFlags::FUNC_FULL_SIMD_MODE);
+ FI.UsesWave32 = !!(Flags & AMDGPU::FuncInfoFlags::FUNC_WAVE32);
HasScalarAttrs = true;
} else if (Dir == "num_sgpr") {
int64_t Val;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
index ea6cd9587bf0b..294886a9c9483 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
@@ -768,6 +768,8 @@ void AMDGPUTargetAsmStreamer::emitAMDGPUInfo(
Flags |= AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK;
if (Info->UsesFullSIMDMode)
Flags |= AMDGPU::FuncInfoFlags::FUNC_FULL_SIMD_MODE;
+ if (Info->UsesWave32)
+ Flags |= AMDGPU::FuncInfoFlags::FUNC_WAVE32;
OS << "\t\t.amdgpu_flags " << llvm::to_underlying(Flags) << '\n';
OS << "\t\t.amdgpu_num_sgpr " << Info->NumSGPR << '\n';
OS << "\t\t.amdgpu_num_vgpr " << Info->NumArchVGPR << '\n';
@@ -1243,6 +1245,8 @@ void AMDGPUTargetELFStreamer::emitAMDGPUInfo(
Flags |= AMDGPU::FuncInfoFlags::FUNC_HAS_DYN_STACK;
if (Info->UsesFullSIMDMode)
Flags |= AMDGPU::FuncInfoFlags::FUNC_FULL_SIMD_MODE;
+ if (Info->UsesWave32)
+ Flags |= AMDGPU::FuncInfoFlags::FUNC_WAVE32;
EmitU32Entry(AMDGPU::InfoKind::INFO_FLAGS, llvm::to_underlying(Flags));
EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_SGPR, Info->NumSGPR);
EmitU32Entry(AMDGPU::InfoKind::INFO_NUM_VGPR, Info->NumArchVGPR);
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
index 71c20842383c4..e20c5b4b90200 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
@@ -37,6 +37,7 @@ struct FuncInfo {
uint32_t PrivateSegmentSize = 0;
uint32_t Occupancy = 0;
bool UsesFullSIMDMode = false;
+ bool UsesWave32 = false;
bool UsesVCC = false;
bool UsesFlatScratch = false;
bool HasDynStack = false;
diff --git a/llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll b/llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
index 2acd79eeb8982..57e3c65b77b9a 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-link-time-codegen.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -amdgpu-enable-object-linking < %s | FileCheck -check-prefixes=ASM %s --implicit-check-not=.amdgpu_num_agpr
; RUN: llc -mtriple=amdgpu9.00-amd-amdhsa -amdgpu-enable-object-linking -filetype=obj < %s | llvm-readobj -r --syms --sections - | FileCheck -check-prefixes=ELF %s
-; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL %s
-; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+wavefrontsize64 -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL %s
-; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+cumode -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=HALF %s
-; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+cumode,+wavefrontsize64 -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=HALF %s
-; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL %s
-; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=+cumode -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL-WAVE32 %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+wavefrontsize64 -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL-WAVE64 %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+cumode -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=HALF-WAVE32 %s
+; RUN: llc -mtriple=amdgpu11.00-amd-amdhsa -mattr=+cumode,+wavefrontsize64 -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=HALF-WAVE64 %s
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL-WAVE32 %s
+; RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mattr=+cumode -amdgpu-enable-object-linking -filetype=asm < %s | FileCheck -check-prefixes=FULL-WAVE32 %s
; Test that with object linking enabled, external LDS declarations produce
; @abs32 at lo relocations, SHN_AMDGPU_LDS symbols, .amdgpu_lds directives,
@@ -44,20 +44,36 @@
; ASM-DAG: .amdgpu_call device_func
; ASM-DAG: .end_amdgpu_info
-; COM: FUNC_FULL_SIMD_MODE (0x8): set when the function uses full SIMD mode
-; COM: (all four SIMD32s). gfx11 default is full SIMD; +cumode selects half
-; COM: SIMD and clears the flag. gfx1250 is always full SIMD, even with
-; COM: +cumode. Checked for both +wavefrontsize32 (default) and
-; COM: +wavefrontsize64 on gfx11.
-; FULL: .amdgpu_info device_func
-; FULL-NEXT: .amdgpu_flags 8
-; FULL: .amdgpu_info test_kernel
-; FULL-NEXT: .amdgpu_flags 8
-
-; HALF: .amdgpu_info device_func
-; HALF-NEXT: .amdgpu_flags 0
-; HALF: .amdgpu_info test_kernel
-; HALF-NEXT: .amdgpu_flags 0
+; COM: FUNC_FULL_SIMD_MODE (0x8) tracks the SIMD mode and FUNC_WAVE32 (0x10)
+; COM: tracks the wave size. gfx11 defaults to full SIMD (all four SIMD32s) and
+; COM: wave32; +cumode selects half SIMD and +wavefrontsize64 selects wave64.
+; COM: gfx1250 is always full SIMD, even with +cumode. The kernel and the device
+; COM: function share the same subtarget-derived flags, so both .amdgpu_flags
+; COM: entries carry the same value in each run.
+
+; COM: FULL_SIMD_MODE | WAVE32 = 0x8 | 0x10 = 24.
+; FULL-WAVE32: .amdgpu_info device_func
+; FULL-WAVE32-NEXT: .amdgpu_flags 24
+; FULL-WAVE32: .amdgpu_info test_kernel
+; FULL-WAVE32-NEXT: .amdgpu_flags 24
+
+; COM: FULL_SIMD_MODE only = 0x8 = 8.
+; FULL-WAVE64: .amdgpu_info device_func
+; FULL-WAVE64-NEXT: .amdgpu_flags 8
+; FULL-WAVE64: .amdgpu_info test_kernel
+; FULL-WAVE64-NEXT: .amdgpu_flags 8
+
+; COM: WAVE32 only = 0x10 = 16.
+; HALF-WAVE32: .amdgpu_info device_func
+; HALF-WAVE32-NEXT: .amdgpu_flags 16
+; HALF-WAVE32: .amdgpu_info test_kernel
+; HALF-WAVE32-NEXT: .amdgpu_flags 16
+
+; COM: neither set = 0.
+; HALF-WAVE64: .amdgpu_info device_func
+; HALF-WAVE64-NEXT: .amdgpu_flags 0
+; HALF-WAVE64: .amdgpu_info test_kernel
+; HALF-WAVE64-NEXT: .amdgpu_flags 0
; SHN_AMDGPU_LDS directives.
; ASM-DAG: .amdgpu_lds lds_large, 256, 16
diff --git a/llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s b/llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s
index 7f81913a5cbb5..a13992cae5a8f 100644
--- a/llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s
+++ b/llvm/test/MC/AMDGPU/amdgpu-info-roundtrip.s
@@ -31,11 +31,11 @@ addr_taken_func:
.globl extern_func
-// COM: Kernel: flags=15 (VCC|FLAT_SCRATCH|HAS_DYN_STACK|FULL_SIMD_MODE), resources,
-// COM: call edge, use edge, indirect call, and type ID. Non-zero AGPR to verify
-// COM: conditional emission.
+// COM: Kernel: flags=31 (VCC|FLAT_SCRATCH|HAS_DYN_STACK|FULL_SIMD_MODE|WAVE32),
+// COM: resources, call edge, use edge, indirect call, and type ID. Non-zero AGPR
+// COM: to verify conditional emission.
.amdgpu_info my_kernel
- .amdgpu_flags 15
+ .amdgpu_flags 31
.amdgpu_num_sgpr 33
.amdgpu_num_vgpr 32
.amdgpu_num_agpr 4
@@ -69,7 +69,7 @@ addr_taken_func:
.end_amdgpu_info
// ASM: .amdgpu_info my_kernel
-// ASM: .amdgpu_flags 15
+// ASM: .amdgpu_flags 31
// ASM: .amdgpu_num_sgpr 33
// ASM: .amdgpu_num_vgpr 32
// ASM: .amdgpu_num_agpr 4
More information about the llvm-branch-commits
mailing list