[llvm-branch-commits] [llvm] 9beff35 - [AArch64] Use NoSchedPred for SME instructions in C1 scheduling models.

[Tobias Hieta via llvm-branch-commits]

Author: David Green
Date: 2026-09-05T09:12:09+02:00
New Revision: 9beff35f67c1aa2a57a6d9a220f47c35d21bdb79

URL: https://github.com/llvm/llvm-project/commit/9beff35f67c1aa2a57a6d9a220f47c35d21bdb79
DIFF: https://github.com/llvm/llvm-project/commit/9beff35f67c1aa2a57a6d9a220f47c35d21bdb79.diff

LOG: [AArch64] Use NoSchedPred for SME instructions in C1 scheduling models.

We can have the scheduling model enabled without SME using -mtune, which means
that no scheduling information was persent for any instructions that execute in
either SME or the core. AFAICT the predicate should be NoSchedPred, as any
instructions should be using the non-streaming scheduling info when not in a
SME function.

This is a cherry-pick of f33ef3a26db25f9a4b75a25af6527304bc03fcb8,
modified to remove the Pro change not present in the llvm-23 branch.

Fixes #220070
Fixes #220067

Added: 
    llvm/test/CodeGen/AArch64/misched-c1sme.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
index f4abd2a9689fd..f36cf50f4abc9 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
@@ -174,7 +174,7 @@ class C1USMEStreamingSchedWrite<SchedWrite StreamingWrite,
                                 SchedWrite SMEWrite>
     : SchedWriteVariant<[
         SchedVar<SMEMCStreamingSchedPred, [StreamingWrite]>,
-        SchedVar<SMESchedPred,            [SMEWrite]>,
+        SchedVar<NoSchedPred,             [SMEWrite]>,
       ]>;
 
 // Detailed CME scheduling derived from the SME2 software optimization guide.

diff  --git a/llvm/test/CodeGen/AArch64/misched-c1sme.ll b/llvm/test/CodeGen/AArch64/misched-c1sme.ll
new file mode 100644
index 0000000000000..a523de0b823a1
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/misched-c1sme.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mtune=c1-nano  | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mtune=c1-premium  | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mtune=c1-pro  | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mtune=c1-ultra  | FileCheck %s
+
+define double @foo() #0 {
+; CHECK-LABEL: foo:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x8, #9221120237041090560 // =0x7ff8000000000000
+; CHECK-NEXT:    fmov d0, x8
+; CHECK-NEXT:    ret
+  ret double +qnan
+}
+
+define double @bar(double %0) #0 {
+; CHECK-LABEL: bar:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi d1, #0000000000000000
+; CHECK-NEXT:    fadd d0, d0, d1
+; CHECK-NEXT:    ret
+  %2 = fadd double %0, 0.000000e+00
+  ret double %2
+}